Robert J Lessard

US Patent:

49311492, Jun 5, 1990

Filed:

Jan 10, 1989

Appl. No.:

7/295684

Inventors:

Roger J. Stierman - Richardson TX
Robert J. Lessard - Garland TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

C25D 502

US Classification:

204 15

Abstract:

This disclosure describes a plating fixture to hold a silicon wafer containing integrated circuits in a metal plating bath. The wafer is coated with photoresist to a thickness equal to the desired bump height and the desired bump locations patterned by standard photolithographic techniques. The wafer is then loaded in the fixture and the fixture placed in the plating bath so that the patterned side of the wafer is facing up and the plating anode is located directly above the wafer. Systems presently on the market have the wafer positioned with the patterned side facing down and the anode located below it, or the wafer faces sideways and the anodes are access from it. These present systems allow air to be entrapped in the pattern of the photoresist, lowering yield by under plating or uneven plating of the bumps on the wafer. This disclosure prevents such yield loss and also allows cleanups on the wafer after it is loaded in the fixture.

US Patent:

50247468, Jun 18, 1991

Filed:

May 14, 1990

Appl. No.:

7/523104

Inventors:

Roger J. Stierman - Garland TX
Robert J. Lessard - Garland TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

C25D 1706

US Classification:

204297W

Abstract:

This disclosure describes a plating fixture to hold a silicon wafer containing integrated circuits in a metal plating bath. The wafer is coated with photoresist to a thickness equal to the desired bump height and the desired bump locations patterened by standard photolithographic techniques. The wafer is then loaded in the fixture and the fixture placed in the plating bath so that the patterned side of the wafer is facing up and the plating anode is located directly above the wafer. Systems presently on the market have the wafer positioned with the patterned side facing down and the anode located below it, or the wafer faces sideways and the anodes are access from it. These present systems allow air to be entrapped in the pattern of the photoresist, lowering yield by under plating or uneven plating of the bumps on the wafer. This disclosure prevents such yield loss and also allows cleanups on the wafer after it is loaded in the fixture.

US Patent:

62040944, Mar 20, 2001

Filed:

Feb 2, 1999

Appl. No.:

9/241714

Inventors:

Gregory B. Hotchkiss - Richardson TX
Robert J. Lessard - Garland TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2144
H01L 2148
H01L 2150
B23K 3512

US Classification:

438120

Abstract:

A method for assembling electronic devices by moving particles (12) on an adhesive sheet (35) having a plurality of adhesive areas (30), comprising the steps of loading the particles (12) onto the adhesive sheet (35) and transferring kinetic energy from a mechanical device (39) to the particles (12) for moving the particles (12) is disclosed. The adhesive sheet (35) may be composed of an adhesive coating (22) laminated to a film (24). The particles (12) may be composed of a variety of materials, including minerals and compounds such as solder or polymers.