Robert Andrew Lester

US Patent:

6363439, Mar 26, 2002

Filed:

Dec 7, 1998

Appl. No.:

09/206515

Inventors:

John D. Battles - Tomball TX
Paul B. Rawlins - Spring TX
Robert Allan Lester - Houston TX
Patrick L. Ferguson - Houston TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1314

US Classification:

710 36, 710 45, 710106, 710107, 710110, 710117

Abstract:

A point-to-point serial communication link between a system interface unit and a peripheral bus interface unit is provide. The system bus interface unit may interface between a CPU bus and a peripheral bus, such as the PCI bus, and may be referred to as a north bridge. The system interface unit may also interface to main memory and to an advanced graphics port. The peripheral bus interface unit may interface between a first peripheral bus, such as the PCI bus, and a second peripheral bus, such as an ISA bus, and may be referred to as a south bridge. The serial communication link between the system interface unit and the bus interface unit may be a one wire serial bus that uses a bus clock from the first peripheral bus as a timing reference. This clock may be the PCI clock. The serial communication link may use a single pin on the system interface unit and a single pin on the bus interface unit to transfer commands between the interface units.

US Patent:

6470429, Oct 22, 2002

Filed:

Dec 29, 2000

Appl. No.:

09/752128

Inventors:

Phillip M. Jones - Spring TX
Robert Allan Lester - Tomball TX

Assignee:

Compaq Information Technologies Group, L.P. - Houston TX

International Classification:

G06F 1200

US Classification:

711138, 711141

Abstract:

An apparatus for identifying requests to main memory as non-cacheable in a computer system with multiple processors includes a main memory, memory cache, processor and cache coherence directory all coupled to a host bridge unit (North bridge). The processor transmits requests for data to the main memory via the host bridge unit. The host bridge unit includes a cache coherence controller that implements a protocol to maintain the coherence of data stored in each of the processor caches in the computer system. A cache coherence directory is connected to the cache coherence controller. After receiving the request for data from main memory, the host bridge unit identifies requests for data to main memory as cacheable or non-cacheable. If the data is non-cacheable, then the host bridge unit does not request the cache coherence controller to perform a cache coherence directory lookup to maintain the coherence of the data.

US Patent:

6608564, Aug 19, 2003

Filed:

Jan 25, 2001

Appl. No.:

09/770100

Inventors:

Christian H. Post - Spring TX
George D. Megason - Spring TX
Brett D. Roscoe - Tomball TX
Paul Santeler - Cypress TX
John M. MacLaren - Cypress TX
John E. Larson - Houston TX
Jeffery Galloway - The Woodlands TX
Siamak Tavallaei - Spring TX
Tim W. Majni - Woodlands TX
Robert Allan Lester - Tomball TX
Anisha Anand - Houston TX
Eric Rose - Austin TX

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G08B 2300

US Classification:

3406935, 3406939, 34069312

Abstract:

A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.

US Patent:

6715116, Mar 30, 2004

Filed:

Jan 25, 2001

Appl. No.:

09/769958

Inventors:

Robert A. Lester - Tomball TX
John M. MacLaren - Cypress TX
Patrick L. Ferguson - Cypress TX
John E. Larson - Houston TX

Assignee:

Hewlett-Packard Company, L.P. - Houston TX

International Classification:

G11C 2900

US Classification:

714718, 714763

Abstract:

A system and technique for detecting data errors in a memory device. More specifically, data errors in a memory device are detected by initiating an internal READ command or verify operation from a set of logic which is internal to the memory system in which the memory devices reside. Rather than relying on a READ command to be issued from an external device, via a host controller, the verify logic initiates verify routine in response to an event such as an operator instruction, hot-plug operation, or a periodic schedule. By implementing the verify operation, the system does not rely on external READ commands to verify data integrity. The verify routine may rely on typical ECC error logging mechanisms and may be used in a RAID memory architecture. Further, the verify routine may be used in conjunction with other error logging and correction logic, as well as scrubbing logic.

US Patent:

6747563, Jun 8, 2004

Filed:

May 14, 2003

Appl. No.:

10/437567

Inventors:

Christian H. Post - Spring TX
George D. Megason - Spring TX
Brett D. Roscoe - Tomball TX
Paul Santeler - Cypress TX
John M. MacLaren - Cypress TX
John E. Larson - Houston TX
Jeffery Galloway - The Woodlands TX
Siamak Tavallaei - Spring TX
Tim W. Majni - Woodlands TX
Robert Allan Lester - Tomball TX
Anisha Anand - Houston TX
Eric Rose - Austin TX

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G08B 2300

US Classification:

3406935, 3406939, 34069312

Abstract:

A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.

US Patent:

6854070, Feb 8, 2005

Filed:

Jan 25, 2001

Appl. No.:

09/769978

Inventors:

Jerome J. Johnson - Spring TX, US
John M. MacLaren - Cypress TX, US
Robert A. Lester - Tomball TX, US
John E. Larson - Houston TX, US
Gary J. Piccirillo - Cypress TX, US
Christian H. Post - Spring TX, US
Jeffery Galloway - The Woodlands TX, US
Ho M. Lai - Spring TX, US
Anisha Anand - Houston TX, US
Eric Rose - Austin TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F011/00

US Classification:

714 5, 714 7, 710302, 711115

Abstract:

A method of adding memory capacity to a computer system. The computer system comprises a redundant memory system including a plurality of memory cartridges. By powering-down a memory cartridge, adding an additional memory module to the memory cartridge, and powering-up the memory cartridge for each memory cartridge in the system, the system can transition from a redundant mode of operation to a non-redundant mode of operation for each power-down, thus allowing the computer system to remain functional during the addition of the memory module. Alternatively, memory cartridges with higher memory capacity than those currently present in the computer system can be used to replace existing memory cartridges in the computer system, using the same techniques.

US Patent:

6961800, Nov 1, 2005

Filed:

Sep 28, 2001

Appl. No.:

09/967155

Inventors:

Robert A. Lester - Tomball TX, US
Kenneth T. Chin - Cypress TX, US
Jim Blocker - Cypress TX, US
John E. Larson - Houston TX, US
Phillip M. Jones - Spring TX, US
Paul B. Rawlins - Spring TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F013/36

US Classification:

710306, 710310

Abstract:

Methods for improving processor performance. Specifically, by reducing some of the latency cycles within a host controller, request processing speed can be improved. One technique for improving processing speed involves initiating a deferred reply transaction before the data is available from a memory controller. A second technique involves anticipating the need to transition from a block next request (BNR) state to a bus priority request (BPRI) state, thereby eliminating the need to wait for a request check to determine if the BPRI state must be implemented.

US Patent:

6975241, Dec 13, 2005

Filed:

May 14, 2003

Appl. No.:

10/438150

Inventors:

Christian H. Post - Spring TX, US
George D. Megason - Spring TX, US
Brett D. Roscoe - Tomball TX, US
Paul Santeler - Cypress TX, US
John M. MacLaren - Cypress TX, US
John E. Larson - Houston TX, US
Jeffery Galloway - The Woodlands TX, US
Siamak Tavallaei - Spring TX, US
Tim W. Majni - Woodlands TX, US
Robert Allan Lester - Tomball TX, US
Anisha Anand - Houston TX, US
Eric Rose - Austin TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G08B023/00

US Classification:

3406935, 3406939, 34069312

Abstract:

A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.