Robert S Lester

US Patent:

6356972, Mar 12, 2002

Filed:

Jan 19, 2001

Appl. No.:

09/765773

Inventors:

Kenneth T. Chin - Cypress TX
Clarence K. Coffee - Pembroke Pines FL
Michael J. Collins - Tomball TX
Jerome J. Johnson - Spring TX
Phillip M. Jones - Spring TX
Robert A. Lester - Houston TX
Gary J. Piccirillo - Cypress TX

Assignee:

Compaq Information Technologies Group, LP - Houston TX

International Classification:

G06F 1314

US Classification:

710310

Abstract:

A computer is provided having a bus interface unit coupled between a processor bus, a peripheral bus, and a memory bus. The bus interface unit includes a processor controller linked to the processor bus for controlling the transfer of cycles from the processor to the peripheral bus and memory bus. Those cycles are initially forwarded as a request, whereby the processor controller includes a memory request queue separate from a peripheral request queue. Requests from the memory and peripheral request queues can be de-queued concurrently to the memory and peripheral buses. This enhances throughput of read and write requests; however, proper ordering of data returned as a result of read requests and data transferred as a result of write requests must be ensured. An in-order queue is also present in the processor controller which records the order in which the requests are dispatched to the peripheral and memory buses from the peripheral and memory request queues. Data ensuing from the request can be re-ordered and presented to the destination based on the current pointer position within the in-order queue.

US Patent:

6363439, Mar 26, 2002

Filed:

Dec 7, 1998

Appl. No.:

09/206515

Inventors:

John D. Battles - Tomball TX
Paul B. Rawlins - Spring TX
Robert Allan Lester - Houston TX
Patrick L. Ferguson - Houston TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1314

US Classification:

710 36, 710 45, 710106, 710107, 710110, 710117

Abstract:

A point-to-point serial communication link between a system interface unit and a peripheral bus interface unit is provide. The system bus interface unit may interface between a CPU bus and a peripheral bus, such as the PCI bus, and may be referred to as a north bridge. The system interface unit may also interface to main memory and to an advanced graphics port. The peripheral bus interface unit may interface between a first peripheral bus, such as the PCI bus, and a second peripheral bus, such as an ISA bus, and may be referred to as a south bridge. The serial communication link between the system interface unit and the bus interface unit may be a one wire serial bus that uses a bus clock from the first peripheral bus as a timing reference. This clock may be the PCI clock. The serial communication link may use a single pin on the system interface unit and a single pin on the bus interface unit to transfer commands between the interface units.

US Patent:

6470429, Oct 22, 2002

Filed:

Dec 29, 2000

Appl. No.:

09/752128

Inventors:

Phillip M. Jones - Spring TX
Robert Allan Lester - Tomball TX

Assignee:

Compaq Information Technologies Group, L.P. - Houston TX

International Classification:

G06F 1200

US Classification:

711138, 711141

Abstract:

An apparatus for identifying requests to main memory as non-cacheable in a computer system with multiple processors includes a main memory, memory cache, processor and cache coherence directory all coupled to a host bridge unit (North bridge). The processor transmits requests for data to the main memory via the host bridge unit. The host bridge unit includes a cache coherence controller that implements a protocol to maintain the coherence of data stored in each of the processor caches in the computer system. A cache coherence directory is connected to the cache coherence controller. After receiving the request for data from main memory, the host bridge unit identifies requests for data to main memory as cacheable or non-cacheable. If the data is non-cacheable, then the host bridge unit does not request the cache coherence controller to perform a cache coherence directory lookup to maintain the coherence of the data.

US Patent:

6505260, Jan 7, 2003

Filed:

Feb 15, 2001

Appl. No.:

09/784690

Inventors:

Kenneth T. Chin - Cypress TX
C. Kevin Coffee - Pembroke Pines FL
Michael J. Collins - Pleasonton CA
Jerome J. Johnson - Spring TX
Phillip M. Jones - Spring TX
Robert A. Lester - Houston TX
Gary J. Piccirillo - Cypress TX
Jeffrey C. Stevens - Spring TX

Assignee:

Compaq Information Technologies Group, L.P. - Houston TX

International Classification:

G06F 1318

US Classification:

710 41, 710 42, 711151

Abstract:

A computer system includes an adaptive memory arbiter for prioritizing memory access requests, including a self-adjusting, programmable request-priority ranking system. The memory arbiter adapts during every arbitration cycle, reducing the priority of any request which wins memory arbitration. Thus, a memory request initially holding a low priority ranking may gradually advance in priority until that request wins memory arbitration. Such a scheme prevents lower-priority devices from becoming âmemory-starved. â Because some types of memory requests (such as refresh requests and memory reads) inherently require faster memory access than other requests (such as memory writes), the adaptive memory arbiter additionally integrates a nonadjustable priority structure into the adaptive ranking system which guarantees faster service to the most urgent requests. Also, the adaptive memory arbitration scheme introduces a flexible method of adjustable priority-weighting which permits selected devices to transact a programmable number of consecutive memory accesses without those devices losing request priority.

US Patent:

6608564, Aug 19, 2003

Filed:

Jan 25, 2001

Appl. No.:

09/770100

Inventors:

Christian H. Post - Spring TX
George D. Megason - Spring TX
Brett D. Roscoe - Tomball TX
Paul Santeler - Cypress TX
John M. MacLaren - Cypress TX
John E. Larson - Houston TX
Jeffery Galloway - The Woodlands TX
Siamak Tavallaei - Spring TX
Tim W. Majni - Woodlands TX
Robert Allan Lester - Tomball TX
Anisha Anand - Houston TX
Eric Rose - Austin TX

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G08B 2300

US Classification:

3406935, 3406939, 34069312

Abstract:

A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.

US Patent:

6640282, Oct 28, 2003

Filed:

Jan 25, 2001

Appl. No.:

09/769716

Inventors:

John M. MacLaren - Cypress TX
Jerome J. Johnson - Spring TX
Robert A. Lester - Tomball TX
Gary J. Piccirillo - Cypress TX
John E. Larson - Houston TX
Christian H. Post - Spring TX
Jeffery Galloway - The Woodlands TX
Ho M. Lai - Spring TX
Eric Rose - Austin TX

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1216

US Classification:

711115, 711157, 710302, 365 52, 365 63, 365226

Abstract:

The control logic for a hot-pluggable memory cartridge for use in a redundant memory system. To implement a hot-pluggable memory cartridge in a redundant memory system, control logic to control the sequence of events for powering-up and powering-down a memory cartridge is provided.

US Patent:

6715116, Mar 30, 2004

Filed:

Jan 25, 2001

Appl. No.:

09/769958

Inventors:

Robert A. Lester - Tomball TX
John M. MacLaren - Cypress TX
Patrick L. Ferguson - Cypress TX
John E. Larson - Houston TX

Assignee:

Hewlett-Packard Company, L.P. - Houston TX

International Classification:

G11C 2900

US Classification:

714718, 714763

Abstract:

A system and technique for detecting data errors in a memory device. More specifically, data errors in a memory device are detected by initiating an internal READ command or verify operation from a set of logic which is internal to the memory system in which the memory devices reside. Rather than relying on a READ command to be issued from an external device, via a host controller, the verify logic initiates verify routine in response to an event such as an operator instruction, hot-plug operation, or a periodic schedule. By implementing the verify operation, the system does not rely on external READ commands to verify data integrity. The verify routine may rely on typical ECC error logging mechanisms and may be used in a RAID memory architecture. Further, the verify routine may be used in conjunction with other error logging and correction logic, as well as scrubbing logic.

US Patent:

6747563, Jun 8, 2004

Filed:

May 14, 2003

Appl. No.:

10/437567

Inventors:

Christian H. Post - Spring TX
George D. Megason - Spring TX
Brett D. Roscoe - Tomball TX
Paul Santeler - Cypress TX
John M. MacLaren - Cypress TX
John E. Larson - Houston TX
Jeffery Galloway - The Woodlands TX
Siamak Tavallaei - Spring TX
Tim W. Majni - Woodlands TX
Robert Allan Lester - Tomball TX
Anisha Anand - Houston TX
Eric Rose - Austin TX

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G08B 2300

US Classification:

3406935, 3406939, 34069312

Abstract:

A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.