Robert C Lester

US Patent:

6766469, Jul 20, 2004

Filed:

Jan 25, 2001

Appl. No.:

09/769783

Inventors:

John E. Larson - Houston TX
John M. MacLaren - Cypress TX
Jerome J. Johnson - Spring TX
Gary J. Piccirillo - Cypress TX
Robert A. Lester - Tomball TX
Christian H. Post - Spring TX
Jeffery Galloway - The Woodlands TX
Anisha Anand - Houston TX
Ho M. Lai - Spring TX
Eric Rose - Austin TX

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1100

US Classification:

714 7, 714 5, 711115, 710302

Abstract:

A method of replacing a memory module in a computer system. Specifically, a method for replacing a memory module in a segment of a redundant memory system, without powering-down the memory system.

US Patent:

6823424, Nov 23, 2004

Filed:

Sep 28, 2001

Appl. No.:

09/966666

Inventors:

John E. Larson - Houston TX
Robert A. Lester - Tomball TX
Elizabeth A. Richard - Houston TX

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1300

US Classification:

711114, 714 7, 713113, 713302

Abstract:

A technique for selecting events associated with a hot-plug operation. More specifically, a programmable configuration register may be used to provide a mechanism for periodically scheduling requests associated with a hot-plug operation, such as initialization, rebuild, and verify requests. An arbiter is provided to facilitate an ordered access to a memory system. A user can select a periodic interval such that hot-plug requests are periodically executed during the execution of normal requests through the arbiter. The user-selectable interval may be dependent on the specific application of the system and the importance of operating in a redundant mode.

US Patent:

6832340, Dec 14, 2004

Filed:

Jan 25, 2001

Appl. No.:

09/769959

Inventors:

John E. Larson - Houston TX
John M. MacLaren - Cypress TX
Robert A. Lester - Tomball TX
Gary J. Piccirillo - Cypress TX
Jerome J. Johnson - Spring TX
Patrick L. Ferguson - Cypress TX

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1100

US Classification:

714 42, 714718

Abstract:

A system and technique for correcting data errors in a memory device. More specifically, data errors in a memory device are corrected by scrubbing the corrupted memory device. Generally, a host controller delivers a READ command to a memory controller. The memory controller receives the request and retrieves the data from a memory sub-system. The data is delivered to the host controller. If an error is detected, a scrub command is induced through the memory controller to rewrite the corrected data through the memory sub-system. Once a scrub command is induced, an arbiter schedules the scrub in the queue. Because a significant amount of time can occur before initial read in the scrub write back to the memory, an additional controller may be used to compare all subsequent READ and WRITE commands to those scrubs scheduled in the queue. If a memory location is rewritten with new data prior to scheduled scrub corresponding to the same address location, the controller will cancel the scrub to that particular memory location.

US Patent:

7155568, Dec 26, 2006

Filed:

Sep 29, 2001

Appl. No.:

09/967610

Inventors:

Elizabeth Anne Richard - Houston TX, US
John Edward Larson - Houston TX, US
Robert Allan Lester - Tomball TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 12/00
G06F 12/12

US Classification:

711114

Abstract:

A transaction generator generates memory transactions identical to processor memory transactions to initialize, rebuild, and verify memory added or replaced during operation of a computer system configured for RAID memory. The transactions read and rewrite the correct value for replaced memory and write a known good value for added memory. Memory writes are verified by a read after the write transaction. The transaction generator is a state machine. A first counter is used for holding memory addresses of the transactions, automatically incrementing after each transaction. A second counter can throttle the generation of transactions by controlling the incrementation speed of the first counter. Transactions generated by the transaction generator have a transaction identifier, selected from a pool of available transaction identifiers. The transactions can complete out of order.

US Patent:

59147270, Jun 22, 1999

Filed:

Sep 9, 1997

Appl. No.:

8/925773

Inventors:

Ronald T. Horan - Houston TX
Phillip M. Jones - Spring TX
Gregory N. Santos - Cypress TX
Robert Allan Lester - Houston TX
Robert C. Elliott - Houston TX

Assignee:

Compaq Computer Corp. - Houston TX

International Classification:

G06F 1516

US Classification:

345503

Abstract:

A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. Contiguous virtual memory address space must be allocated for the AGP device within the addressable memory space of the computer system, typically 4 gigabytes using 32 bit addressing. The required amount of virtual memory address space for AGP is determined from the AGP device and the information is put into a register of the core logic so that the computer system software may allocate the required amount of memory and assign a base address thereto during computer system startup or POST. An AGP Valid bit is set to indicate whether an AGP device is present or not.

US Patent:

H4731, Jun 7, 1988

Filed:

Jan 9, 1985

Appl. No.:

6/689752

Inventors:

Robert S. Lester - Houston TX
Charles E. Smith - Houston TX
Timothy C. Hurley - Stafford TX
Terrence A. Onda - Houston TX

Assignee:

Shell Oil Company - Houston TX

International Classification:

G01N 1502
G01N 2101
C12Q 118

US Classification:

356335

Abstract:

A method and apparatus for counting small particles in a capillary tube is provided. The method and apparatus detect changes in the intensity of the direct beam passing perpendicularly through the capillary tube to count such small particles.

US Patent:

60783389, Jun 20, 2000

Filed:

Mar 11, 1998

Appl. No.:

9/038412

Inventors:

Ronald T. Horan - Houston TX
Phillip M. Jones - Spring TX
Gregory N. Santos - Cypress TX
Robert Allan Lester - Houston TX
Gary J. Piccirillo - Cypress TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1316

US Classification:

345521

Abstract:

A computer system having a core logic chipset that interconnects a processor(s), a system memory and peripheral device agents. The core logic chipset has a programmable memory access arbiter that may be programmed to optimize accesses by the computer system processor(s) and agents to the system memory for best computer system performance. The memory access arbiter may be programmed specifically for each system agent. An access count register may be incorporated into the core logic chipset wherein each system agent may be represented by a portion of the access count register. The values programmed into the portions of the access count register determine how many memory accesses the associated agent may take before another agent is granted a memory access, and how many cachelines may be transferred during a memory access.

US Patent:

54527619, Sep 26, 1995

Filed:

Oct 31, 1994

Appl. No.:

8/331802

Inventors:

David Beard - Houston TX
Robert A. Lester - Houston TX

Assignee:

Western Atlas International, Inc. - Houston TX

International Classification:

E21B 4300

US Classification:

166250

Abstract:

An apparatus and method for digitally processing signals received by an induction logging tool having a transmitter and a plurality of receivers. An oscillating signal is provided to the transmitter, which causes eddy currents to flow in a surrounding formation. The magnitudes of the eddy currents are proportional to the conductivity of the formation. The eddy currents in turn induce voltages in the receivers. The received voltages are digitized at a sampling rate well above the maximum frequency of interest. The digitizing window is synchronized to a cycle of the oscillating current signal. Corresponding samples obtained in each cycle are cumulatively summed over a large number of such cycles. The summed samples form a stacked signal. Stacked signals generated for corresponding receiver coils are transmitted to a computer for spectral analysis.