Robert J Lodi

US Patent:

40854604, Apr 18, 1978

Filed:

Apr 5, 1976

Appl. No.:

5/673559

Inventors:

Robert J. Lodi - Tewksbury MA

Assignee:

Sperry Rand Corporation - New York NY

International Classification:

G11C 700

US Classification:

365230

Abstract:

The decoder buffer is utilized in a memory system for an array of variable threshold MNOS transistor memory cells arranged in word rows. The gate electrodes of the memory transistors comprising each word row is coupled via a word line to the output of a decoder buffer. Inputs to the decoder buffers are provided from address decoder and inverter circuits in response to memory address inputs. FET control circuitry is included for selectively providing operating voltages to the decoder buffers in accordance with the various memory functions performed. Each decoder buffer comprises first, second and third fixed threshold field effect transistors, the first and second transistors being serially connected with respect to each other, forming a junction therebetween which is coupled to the associated one of the memory word lines. The third transistor is connected between the gate of the first transistor and the junction between the first and second transistors, the associated address decoder output line being connected to the gate of the first transistor. The control circuits provide operating voltages selectively to the electrodes of the first and second transistors opposite the junction and to the gate electrode of the third transistor for controlling the buffers in the various modes of the memory.

US Patent:

39710017, Jul 20, 1976

Filed:

Jun 10, 1974

Appl. No.:

5/477723

Inventors:

Robert J. Lodi - Tewksbury MA

Assignee:

Sperry Rand Corporation - New York NY

International Classification:

G11C 506
G11C 1140

US Classification:

340173R

Abstract:

A monolithic integrated circuit, fully decoded memory comprises a rectangular array of variable threshold field effect transistors organized into a plurality of multi-bit words. Binary address inputs to the memory are decoded by a field effect transistor decoder into a plurality of word selection lines each of which activates an address buffer circuit. Each address buffer circuit, in turn, drives a word line of the memory array. In accordance with the word line selected by the decoder the activated buffer circuit directs reading or writing voltages to the transistors comprising the memory words. All of the buffer circuits additionally are connected to a common terminal for clearing all of the memory transistors to a predetermined state by the application to the common terminal of a large magnitude voltage of a predetermined polarity. The address decoder, the buffer and the memory array, as well as control and input/output control and buffer field effect transistor circuits, are fabricated on a common substrate with means provided to isolate the substrate of the address buffer transistors from the remainder of the substrate so that the bulk clearing function of simultaneously placing all of the memory transistors into a predetermined state can be performed.

US Patent:

40992640, Jul 4, 1978

Filed:

Oct 28, 1976

Appl. No.:

5/736651

Inventors:

Robert J. Lodi - Tewksbury MA

Assignee:

Sperry Rand Corporation - New York NY

International Classification:

G11C 1140

US Classification:

365189

Abstract:

An illustrative embodiment of the invention provides a substantially non-destructive interrogation circuit for a memory cell such as a variable threshold insulated gate field effect memory transistor device whereby the circuit generates a fixed current for interrogation of the memory transistor such that the disturb voltage, the voltage impressed across the insulator of the memory transistor during interrogation, is minimized and is a function of the current and the gain of the memory device and not the threshold of the memory device. Moreover the disturb voltage is readily calculable and is equal for all interrogations and, therefore, enables one to calculate the maximum number of interrogations of a memory cell before the disturb voltage destroys the memory threshold of the memory cell and rewriting of the data therein must be performed. In addition, a sense latch circuit provides means for sensing the memory data of the memory cell without applying an additional disturb potential to the device.

US Patent:

41225457, Oct 24, 1978

Filed:

Jan 3, 1978

Appl. No.:

5/866573

Inventors:

Robert J. Lodi - Tewksbury MA

Assignee:

Sperry Rand Corporation - New York NY

International Classification:

G11C 1140

US Classification:

365186

Abstract:

The present invention relates to a memory circuit including an array of inversion controlled switches arranged in an arbitrary number of rows and columns. Each inversion controlled switch is provided with emitter, base and collector terminals, and is characterized by first and second impedance states between its emitter and collector terminals. The memory circuit further includes voltage means coupled with the inversion controlled switches of the array for applying a selectively controllable voltage across the emitter and collector terminals of these switches in selected ones of the rows; a plurality of rectifier means each coupled with the base terminal of a respective inversion controlled switch; current means coupled with the rectifier means for applying a current level to the base terminals of the inversion controlled switches in selected ones of the columns through the rectifier means; and data sensing means coupled with the inversion controlled switches in individual ones of the columns for sensing the impedance state of a selected one of the switches in a respective one of the columns.