Robert William Maher

US Patent:

6343363, Jan 29, 2002

Filed:

May 12, 2000

Appl. No.:

09/570155

Inventors:

Robert Maher - Carrollton TX
Margaret R. Herubin - Coppell TX
Mark Bluhm - Carrollton TX

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G06F 132

US Classification:

713324

Abstract:

A technique for invoking a low power operational mode in response to a halt instruction is used in a computer system that includes a processor coupled to external logic. The processor includes at least (i) a pipeline subcircuit to execute programmed instructions, including halt instructions, (ii) an interrupt handling subcircuit to handle interrupts generated by external interrupt logic, and (iii) clock generator circuitry that supplies clock signals to the pipeline and interrupt handling subcircuits. In response to execution of a halt instruction, the processor (i) enters the low power operational mode in which power consumption is reduced at least for the pipeline subcircuit, but without stopping the supply of clock signals to the interrupt handling subcircuit, and (ii) generates an acknowledgement signal to the external logic indicating that the clock signals to the pipeline subcircuit are being stopped, thereby entering the low power operational mode. In a preferred embodiment, the low power operational mode is entered by stopping the clock generator circuitry from supplying clock signals to the pipeline subcircuit, but not to the interrupt handling subcircuit. To resume normal processing, the interrupt handling subcircuit responds to an interrupt generated by the external logic by causing the clock generator circuitry to resume supplying clock signals to the pipeline subcircuit.

US Patent:

6694443, Feb 17, 2004

Filed:

Feb 8, 2001

Appl. No.:

09/779150

Inventors:

Robert Maher - Carrollton TX
Margaret R. Herubin - Coppell TX
Mark Bluhm - Carrollton TX

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G06F 130

US Classification:

713323, 713310, 713322

Abstract:

Power consumption reduction control circuitry external and coupled to a processor used to execute instructions for data processing. A power management control signal is provided to the processor in accordance with conditions associated with the processor being operated in normal and reduced power consumption modes of operation, and an acknowledgement signal indicative of such reduced power consumption mode of operation is returned in correspondence with the power management control signal.

US Patent:

6721894, Apr 13, 2004

Filed:

Aug 9, 2002

Appl. No.:

10/216615

Inventors:

Robert Maher - Carrollton TX
Margaret R. Herubin - Coppell TX
Mark Bluhm - Carrollton TX

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G06F 126

US Classification:

713323, 713310

Abstract:

In accordance with the presently claimed invention, power consumption reduction control is provided to a processor used to execute instructions for data processing. A power management control signal is provided to the processor in accordance with conditions associated with the processor being operated in normal and reduced power consumption modes of operation, and an acknowledgement signal indicative of such reduced power consumption mode of operation is returned in correspondence with the power management control signal.

US Patent:

6910141, Jun 21, 2005

Filed:

Feb 23, 2004

Appl. No.:

10/784835

Inventors:

Robert Maher - Carrollton TX, US
Margaret R. Herubin - Coppell TX, US
Mark Bluhm - Carrollton TX, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G06F001/26

US Classification:

713323, 713310, 713322, 713324, 712220

Abstract:

A pipelined data processor with signal-initiated power management control in which a plurality of subcircuits, including pipeline subcircuitry, and circuitry for generating and controlling at least one clock signal are responsive to at least one control signal by disabling a clock signal to the pipeline subcircuitry.

US Patent:

6978390, Dec 20, 2005

Filed:

Feb 23, 2004

Appl. No.:

10/784672

Inventors:

Robert Maher - Carrollton TX, US
Margaret R. Herubin - Coppell TX, US
Mark Bluhm - Carrollton TX, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G06F001/26

US Classification:

713323, 713322, 713324, 712220

Abstract:

A pipelined data processor with instruction-initiated power management control in which a plurality of subcircuits, including pipeline subcircuitry and circuitry for generating and controlling at least one clock signal are responsive to an instruction executed by the pipeline subcircuitry by selectively disabling a clock signal to the pipeline subcircuitry.

US Patent:

7000132, Feb 14, 2006

Filed:

Feb 23, 2004

Appl. No.:

10/784396

Inventors:

Robert Maher - Carrollton TX, US
Margaret R. Herubin - Coppell TX, US
Mark Bluhm - Carrollton TX, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G08F 1/26

US Classification:

713323, 713310, 713322, 713324, 712220

Abstract:

A signal-initiated power management method for a pipelined data processor by which a clock signal to pipeline subcircuitry is selectively disabled in response to at least one control signal.

US Patent:

7062666, Jun 13, 2006

Filed:

Feb 23, 2004

Appl. No.:

10/784834

Inventors:

Robert Maher - Carrollton TX, US
Margaret R. Herubin - Coppell TX, US
Mark Bluhm - Carrollton TX, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G06F 1/26

US Classification:

713324, 713322

Abstract:

A signal-initiated method for suspending operation of a pipelined data processor by selectively disabling a clock signal to pipeline subcircuitry in response to at least one control signal.

US Patent:

7120810, Oct 10, 2006

Filed:

Feb 23, 2004

Appl. No.:

10/784846

Inventors:

Robert Maher - Carrollton TX, US
Margaret R. Herubin - Coppell TX, US
Mark Bluhm - Carrollton TX, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G06F 1/26

US Classification:

713323, 713322, 713324, 712220

Abstract:

An instruction-initiated power management method for a pipelined data processor by which a clock signal to pipeline subcircuitry is selectively disabled in response to an instruction executed by the pipeline subcircuitry.