Robert L Mathews

US Patent:

6381730, Apr 30, 2002

Filed:

Jul 9, 1999

Appl. No.:

09/350966

Inventors:

Li-Fu Chang - Santa Clara CA
Robert G. Mathews - Los Altos CA
Martin G. Walker - Woodside CA

Assignee:

Sequence Design, Inc. - Santa Clara CA

International Classification:

G06F 1750

US Classification:

716 5, 716 4

Abstract:

A novel parasitic extraction system includes an interconnect primitive library that has a parameterized inductance function for at least one conducting layer of the integrated circuit. A parasitic extractor analyzes structures within a selected distance of a selected conductor within the integrated circuit and determines parasitic inductance values for the selected conductor using the parameterized inductance function of the interconnect primitive library. Using this parasitic extraction system, parasitic impedances, including inductance, may be extracted for an integrated circuit layout, thus allowing more accurate modeling and timing analysis of the integrated circuit layout to be obtained.

US Patent:

6403389, Jun 11, 2002

Filed:

Aug 12, 1999

Appl. No.:

09/373923

Inventors:

Robert G. Mathews - Los Altos CA
Shih-tsun A. Chou - Sunnyvale CA
Abhay Dubey - Fremont CA

Assignee:

Sequence Design, Inc. - Santa Clara CA

International Classification:

H01L 2166

US Classification:

438 18, 438 17, 324719, 257 48

Abstract:

A method measures a resistance in a test structure to determine the sheet resistivity of a test structure. In one embodiment, a family of test structures is provided to determine the effective sheet resistivity of a conductor as a function of its width. The method is applicable to conductors in manufacturing processes in which âslotsâ or âislandsâ are created in the conductor to prevent dishing during chemical-mechanical polishing.

US Patent:

6591407, Jul 8, 2003

Filed:

Mar 1, 2000

Appl. No.:

09/516489

Inventors:

Douglas Kaufman - Menlo Park CA
Hazem Almusa - San Jose CA
Vinay Srinivas - Redwood City CA
Donald V. Organ - Saratoga CA
Larry Ke - San Jose CA
Wei Li - Milpitas CA
Japinder Singh - Santa Clara CA
Robert Mathews - Los Altos CA

Assignee:

Sequence Design, Inc. - Santa Clara CA

International Classification:

G06F 1750

US Classification:

716 10, 716 2, 716 3, 716 9

Abstract:

A method and an apparatus are provided for post-layout optimization of an integrated circuit. In one instance, only local transformations accomplished by incremental changes to placement and routing are provided, so as to avoid the costly design iteration loop that requires re-synthesis, re-place and re-route. Optimization can be provided in multiple optimization phases each accomplishing a specified set of transformations. Static timing analysis is performed at the end of each set of local transformations to determine if further optimization steps are required. In one instance, the physical design is first scanned for mismatch between drivers and loads. Then, in a second optimization phase, âhot spotsâ in the physical design are identified for local transformation using a âbidirectional combinational total negative slackâ (BCTNS) algorithm. In subsequent phases, optimization based on meeting setup times and hold times in a critical path are performed.

US Patent:

6643831, Nov 4, 2003

Filed:

Jan 24, 2002

Appl. No.:

10/057165

Inventors:

Li-Fu Chang - Santa Clara CA
Robert G. Mathews - Los Altos CA
Martin G. Walker - Woodside CA

Assignee:

Sequence Design, Inc. - Santa Clara CA

International Classification:

G06F 1750

US Classification:

716 4, 716 5

Abstract:

A novel parasitic extraction system includes an interconnect primitive library that has a parameterized inductance function for at least one conducting layer of the integrated circuit. A parasitic extractor analyzes structures within a selected distance of a selected conductor within the integrated circuit and determines parasitic inductance values for the selected conductor using the parameterized inductance function of the interconnect primitive library. Using this parasitic extraction system, parasitic impedances, including inductance, may be extracted for an integrated circuit layout, thus allowing more accurate modeling and timing analysis of the integrated circuit layout to be obtained.

US Patent:

7222311, May 22, 2007

Filed:

Mar 12, 2003

Appl. No.:

10/387644

Inventors:

Douglas Kaufman - Menlo Park CA, US
Hazem Almusa - San Jose CA, US
Vinay Srinivas - Redwood City CA, US
Donald V. Organ - Saratoga CA, US
Larry Ke - San Jose CA, US
Wei Li - Milpitas CA, US
Japinder Singh - Santa Clara CA, US
Robert Mathews - Los Altos CA, US

Assignee:

Sequence Design, Inc. - Santa Clara CA

International Classification:

G06F 17/50

US Classification:

716 2

Abstract:

A method and an apparatus are provided for post-layout optimization of an integrated circuit. In one instance, only local transformations accomplished by incremental changes to placement and routing are provided, so as to avoid the costly design iteration loop that requires re-synthesis, re-place and re-route. Optimization can be provided in multiple optimization phases each accomplishing a specified set of transformations. Static timing analysis is performed at the end of each set of local transformations to determine if further optimization steps are required. In one instance, the physical design is first scanned for mismatch between drivers and loads. Then, in a second optimization phase, “hot spots” in the physical design are identified for local transformation using a “bidirectional combinational total negative slack” (BCTNS) algorithm. In subsequent phases, optimization based on meeting setup times and hold times in a critical path are performed.

US Patent:

63113120, Oct 30, 2001

Filed:

Sep 23, 1999

Appl. No.:

9/405510

Inventors:

Robert G. Mathews - Los Altos CA
Li-Fu Chang - Santa Clara CA
Xu Yang - Sunnyvale CA

Assignee:

Sequence Design, Inc. - Santa Clara CA

International Classification:

G06F 1750

US Classification:

716 5

Abstract:

A method models conductive regions of a semiconductor substrate in conjunction with conductors in the interconnect structures above the semiconductor substrate. Such a method allows highly accurate extraction of capacitance in planar (e. g. , shallow trench isolation) and non-planar (e. g. , thermal oxide isolation) semiconductor structures. This method is particularly applicable to modeling dummy diffusion regions prevalent in shallow trench isolation structures. An area-perimeter approach simplifies calculation of capacitance without using a 3-dimensional electric field solver. A method is also provided for extracting a capacitance associate with a contact, or a connecting conductor between two conductor layers.

US Patent:

62912542, Sep 18, 2001

Filed:

Feb 4, 1999

Appl. No.:

9/244616

Inventors:

Shih-tsun Alexander Chou - Sunnyvale CA
Robert G. Mathews - Los Altos CA

Assignee:

Sequence Design, Inc. - San Jose CA

International Classification:

G01L 2166

US Classification:

438 18

Abstract:

A method provides estimations of physical interconnect process parameter values in a process for manufacturing integrated circuits. The method includes fabricating test structures each providing a value of a measurable quantity corresponding to a value within a range of values of the physical interconnect process parameters. In some embodiments, the measured value is used to derive the values of the physical interconnect process parameters, either by a numerical method using a field solver, or by a closed-form solution. The values of physical interconnect process parameters involving physical dimensions are also obtained by measuring photomicrographs obtained using a scanning electron microscope from cross sections of test structures. In some embodiments, a family of test structures corresponding to a range of conductor widths and a range of spacings between conductors are measured.

US Patent:

60571713, May 2, 2000

Filed:

Sep 25, 1997

Appl. No.:

8/937393

Inventors:

Shih-tsun Alexander Chou - Sunnyvale CA
Robert G. Mathews - Los Altos CA

Assignee:

Frequency Technology, Inc. - San Jose CA

International Classification:

H01L 2166
G01R 3126

US Classification:

438 15

Abstract:

A method provides estimations of physical interconnect process parameter values in a process for manufacturing integrated circuits. The method includes fabricating test structures each providing a value of a measurable quantity corresponding to a value within a range of values of the physical interconnect process parameters. In some embodiments, the measured value is used to derive the values of the physical interconnect process parameters, either by a numerical method using a field solver, or by a closed-form solution. The values of physical interconnect process parameters involving physical dimensions are also obtained by measuring photomicrographs obtained using a scanning electron microscope from cross sections of test structures. In some embodiments, a family of test structures corresponding to a range of conductor widths and a range of spacings between conductors are measured.