Robert Kelly May

US Patent:

20220413233, Dec 29, 2022

Filed:

Jun 24, 2021

Appl. No.:

17/357788

Inventors:

- Santa Clara CA, US
Kristof Darmawikarta - Chandler AZ, US
Brandon Marin - Gilbert AZ, US
Robert May - Chandler AZ, US
Sri Ranga Sai Boyapati - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G02B 6/42

Abstract:

An optical package comprising an optical die that is electrically coupled to a package substrate, and an optical interconnect adjacent the optical die. The optical interconnect comprises a first polarizing filter adjacent to a first lens, a second polarizing filter adjacent to a second lens; and a film comprising a magnetic material between the first polarizing filter and the second polarizing filter. The second polarizing filter is rotated with respect to the first polarizing filter and the magnetic material is to rotate a polarization vector of light incoming to the optical interconnect. An optical fiber interface port is immediately adjacent to the first lens. The second lens is immediately adjacent to an optical interface of the optical die.

US Patent:

20220319996, Oct 6, 2022

Filed:

Jun 16, 2022

Appl. No.:

17/842600

Inventors:

- Santa Clara CA, US
Adel A. Elsherbini - Chandler AZ, US
Kristof Darmawikarta - Chandler AZ, US
Robert A. May - Chandler AZ, US
Sri Ranga Sai Boyapati - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/538
H01L 25/18
H01L 25/065
H01L 21/48
H01L 23/00
H01L 23/31
H01L 25/00
H01L 23/498

Abstract:

An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.

US Patent:

20220285278, Sep 8, 2022

Filed:

May 24, 2022

Appl. No.:

17/752717

Inventors:

- Santa Clara CA, US
Hiroki TANAKA - Chandler AZ, US
Oscar OJEDA - Chandler AZ, US
Arnab ROY - Chandler AZ, US
Leonel R. ARANA - Phoenix AZ, US
Chung Kwang TAN - Chandler AZ, US
Robert A. MAY - Chandler AZ, US

International Classification:

H01L 23/538
H01L 21/48

Abstract:

Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.

US Patent:

20220223527, Jul 14, 2022

Filed:

Apr 4, 2022

Appl. No.:

17/712944

Inventors:

- Santa Clara CA, US
Hiroki TANAKA - Chandler AZ, US
Robert MAY - Chandler AZ, US
Sameer PAITAL - Chandler AZ, US
Bai NIE - Chandler AZ, US
Jesse JONES - Chandler AZ, US
Chung Kwang Christopher TAN - Chandler AZ, US

International Classification:

H01L 23/538
H01L 23/00
H01L 23/522

Abstract:

Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.

US Patent:

20220199515, Jun 23, 2022

Filed:

Mar 9, 2022

Appl. No.:

17/690964

Inventors:

- Santa Clara CA, US
Jung Kyu HAN - Chandler AZ, US
Ali LEHAF - Phoenix AZ, US
Steve CHO - Chandler AZ, US
Thomas HEATON - Mesa AZ, US
Hiroki TANAKA - Chandler AZ, US
Kristof DARMAWIKARTA - Chandler AZ, US
Robert Alan MAY - Chandler AZ, US
Sri Ranga Sai BOYAPATI - Chandler AZ, US

International Classification:

H01L 23/498
H01L 23/538
H01L 25/18
H01L 21/48
H01L 23/00
H01L 25/00

Abstract:

A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.

US Patent:

20220187549, Jun 16, 2022

Filed:

Dec 15, 2020

Appl. No.:

17/122352

Inventors:

- Santa Clara CA, US
Brandon C. MARIN - Gilbert AZ, US
Robert Alan MAY - Chandler AZ, US
Sri Ranga Sai BOYAPATI - Chandler AZ, US
Srinivas V. PIETAMBARAM - Chandler AZ, US

International Classification:

G02B 6/42

Abstract:

Embodiments disclosed herein include photonics package with Faraday rotators to improve efficiency. In an embodiment, a photonics package comprises a package substrate and a compute die over the package substrate. In an embodiment, the photonics package further comprises a photonics die over the package substrate. In an embodiment, the compute die is communicatively coupled to the photonics die by a bridge in the package substrate. In an embodiment, the photonics package further comprises an integrated heat spreader (IHS) over the package substrate, and a Faraday rotator passing through the IHS and optically coupled to the photonics die.

US Patent:

20220181166, Jun 9, 2022

Filed:

Feb 22, 2022

Appl. No.:

17/677105

Inventors:

- Santa Clara CA, US
Robert May - Chandler AZ, US
Sri Ranga Sai Boyapati - Chandler AZ, US
Srinivas V. Pietambaram - Chandler AZ, US
Chung Kwang Christopher Tan - Portland OR, US
Aleksandar Aleksov - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/48
H01L 23/498

Abstract:

Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.

US Patent:

20220181262, Jun 9, 2022

Filed:

Feb 22, 2022

Appl. No.:

17/677130

Inventors:

- Santa Clara CA, US
Ram Viswanath - Phoenix AZ, US
Xavier Francois Brun - Hillsboro OR, US
Tarek A. Ibrahim - Mesa AZ, US
Jason M. Gamba - Gilbert AZ, US
Manish Dubey - Chandler AZ, US
Robert Alan May - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/538
H01L 23/367
H01L 23/31
H01L 23/00

Abstract:

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.