Robert W Mccarthy

US Patent:

8304867, Nov 6, 2012

Filed:

Nov 1, 2010

Appl. No.:

12/917144

Inventors:

Robert Fabian McCarthy - Dallas TX, US
Stanley Craig Beddingfield - McKinney TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/495

US Classification:

257669, 257673, 257727, 257780, 257786, 257E23169

Abstract:

An integrated circuit (IC) device includes a substrate having a top surface including active circuitry including a plurality of I/O nodes, and a plurality of die pads coupled to the plurality of I/O nodes. A first dielectric layer including first dielectric vias is over the plurality of die pads. A redirect layer (RDL) including a plurality of RDL capture pads is coupled to the plurality of die pads over the first dielectric vias. A second dielectric layer including second dielectric vias is over the plurality of RDL capture pads. At least one of the second dielectric vias is a crack arrest via that has a via shape that includes an apex that faces away from a neutral stress point of the IC die and is oriented along a line from the neutral stress point to the crack arrest via to face in a range of 30 degrees from the line. Under bump metallization (UBM) pads are coupled to the plurality of RDL capture pads over the second dielectric vias, and metal bonding connectors are on the UBM pads.

US Patent:

20090278263, Nov 12, 2009

Filed:

May 9, 2008

Appl. No.:

12/118078

Inventors:

Robert Fabian McCarthy - Dallas TX, US
Stanley Craig Beddingfield - McKinney TX, US

International Classification:

H01L 23/52
G06F 9/455

US Classification:

257778, 716 11, 257E23141

Abstract:

An integrated circuit device includes a functional circuit die with a patterned rewiring layer defining a first rewiring pad and one or more second rewiring pads on opposite sides of a neutral point of the die. The device also includes at least one dielectric layer having bump opening features over the rewiring pads. The device further includes electrically conductive bump pad features formed on the dielectric layer over the bump opening features. The bump pad features make contact with the rewiring pads via the bump opening features. In the device, a center of the bump opening features are laterally offset from a center of the bump pad feature towards a neutral point of the die.

US Patent:

20130119538, May 16, 2013

Filed:

Nov 16, 2011

Appl. No.:

13/297699

Inventors:

Robert Fabian McCarthy - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/498
H01L 21/50
H01L 21/56

US Classification:

257738, 438118, 438113, 257E23069, 257E21499, 257E21502

Abstract:

A method of making a wafer level chip size package (WCSP) comprising providing a die having a first face with a plurality of bond pads thereon, a second face opposite the first face and a plurality of side faces extending between the first face and the second face, at least one of the plurality of side faces having saw induced microcracks therein; and coating at least one of the plurality of side faces with a thin veneer of adhesive that penetrates the microcracks. A WCSP produced by the method is also disclosed.

US Patent:

20130206843, Aug 15, 2013

Filed:

Feb 14, 2012

Appl. No.:

13/396265

Inventors:

Robert Fabian McCarthy - Dallas TX, US

Assignee:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

International Classification:

G06K 19/07
G11C 5/02
H03K 19/00
H01L 21/58

US Classification:

235492, 438106, 365 51, 326 8, 257E21505

Abstract:

An integrated circuit package that includes a first die with a memory positioned physically at a predetermined memory location in the first die; a second die positioned in covering relationship with at least the predetermined memory location in the first die; penetration detection circuitry, positioned at least partially in said second die, that generates a penetration detection signal in response to physical penetration of the second die; and memory circuitry operatively associated with the memory in the first die and the penetration detection circuitry, which is adapted to perform an operation on the memory, such as data erasure, in response to the penetration detection signal.