Robert R Means

US Patent:

6366897, Apr 2, 2002

Filed:

Jul 26, 1999

Appl. No.:

09/361776

Inventors:

Robert W. Means - Rancho Santa Fe CA
Richard Calmbach - San Diego CA

Assignee:

HNC Software, Inc. - San Diego CA

International Classification:

G06F 1518

US Classification:

706 27, 706 39, 706 4

Abstract:

A cortronic neural network defines connections between neurons in a number of regions using target lists, which identify the output connections of each neuron and the connection strength. Neurons are preferably sparsely interconnected between regions. Training of connection weights employs a three stage process, which involves computation of the contribution to the input intensity of each neuron by every currently active neuron, a competition process that determines the next set of active neurons based on their current input intensity, and a weight adjustment process that updates and normalizes the connection weights based on which neurons won the competition process, and their connectivity with other winning neurons.

US Patent:

51386950, Aug 11, 1992

Filed:

Oct 10, 1989

Appl. No.:

7/419040

Inventors:

Robert W. Means - Rancho Santa Fe CA
Horace J. Sklar - Escondido CA

Assignee:

HNC, Inc. - San Diego CA

International Classification:

G06K 964

US Classification:

395 27

Abstract:

A systolic array of processing elements is connected to receive weight inputs and multiplexed data inputs for operation in feedforward, partially-- or fully-connected neural network mode or in cooperative, competitive neural network mode. Feature vector or two-dimensional image data is retrieved from external data memory and is transformed via input look-up table to input data for the systolic array that performs a convolution with kernal values as weight inputs. The convoluted image or neuron outputs from the systolic array are scaled and transformed via output look-up table for storage in the external data memory.

US Patent:

39872920, Oct 19, 1976

Filed:

Jun 2, 1975

Appl. No.:

5/583086

Inventors:

Robert W. Means - San Diego CA

Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC

International Classification:

G06G 719

US Classification:

235181

Abstract:

A circuit for generating a discrete Fourier transform in real time employs a digital and analog shift register, each cell of which is tapped to feed an analog switch. The outputs of the individual analog switches are fed to a summing bus where the switched analog signals combine to form the desired Fourier transform.

US Patent:

54716276, Nov 28, 1995

Filed:

May 26, 1992

Appl. No.:

7/889620

Inventors:

Robert W. Means - Rancho Santa Fe CA
Horace J. Sklar - Escondido CA

Assignee:

HNC, Inc. - San Diego CA

International Classification:

G06K 964

US Classification:

395800

Abstract:

A systolic array of processing elements is connected to receive weight inputs and multiplexed data inputs for operation in two dimension convolution mode, or fully-connected neural network mode, or in cooperative, competitive neural network mode. Feature vector or two-dimensional image data is retrieved from external data memory and is transformed via input look-up table to input data for the systolic array. The convoluted image or outputs from the systolic array are scaled and transformed via output look-up table for storage in the external data memory. The architecture of the system allows it to calculate convolutions of any size within the same physical systolic array, merely by adjusting the programs that control the data flow.