Robert R Moss

US Patent:

6366530, Apr 2, 2002

Filed:

Sep 28, 2001

Appl. No.:

09/965947

Inventors:

David O. Sluiter - Boulder CO
Robert W. Moss - Longmont CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 804

US Classification:

365240, 365233, 365239, 365221, 36518905, 36523006, 36518902

Abstract:

A digital logic circuit, such as a FIFO memory, includes pointers, or indicators, generated in two clock domains, between which information is transferred, to indicate a location in the digital logic circuit for transferring the information into or out of the digital logic circuit within either clock domain. Each pointer is encoded with a â2-hotâ encoded value within one of the clock domains. The 2-hot encoded value of each pointer is sent to the other clock domain to synchronize the pointer to the other clock domain as well as to its original clock domain. Within each clock domain, the pointer generated therein and the pointer received from the other clock domain are used to determine whether the information can be transferred into or out of the digital logic circuit.

US Patent:

6725306, Apr 20, 2004

Filed:

Feb 27, 2002

Appl. No.:

10/083833

Inventors:

Russell B. Stuber - Boulder CO
Robert W. Moss - Longmont CO
David O. Sluiter - Superior CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 1338

US Classification:

710107, 710108, 710110, 710112, 710 57

Abstract:

A slave device includes a queue that receives commands or data from a master device for execution on a first-in, first-out basis. A status register is responsive to the queue to provide a STATUS_FULL signal when the queue is full of commands and a STATUS_EMPTY signal when the queue is empty. A configuration register provides a DEBUG signal identifying a maintenance status of the slave device. A bus control provides a QUEUE_FULL signal in response to either (1) the STATUS_FULL signal or (2) the DEBUG signal and not the STATUS_EMPTY signal to split further commands or stall the data bus.

US Patent:

6910087, Jun 21, 2005

Filed:

Jun 10, 2002

Appl. No.:

10/165921

Inventors:

Russell B. Stuber - Boulder CO, US
Robert W. Moss - Longmont CO, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F013/00
G06F013/14
G06F013/28
G06F013/42

US Classification:

710110, 710 35, 710106, 711167

Abstract:

A slave device includes a command FIFO that stores commands for a device controller on a first-in, first-out basis to execute a read or write transaction. Commands are received from the data bus by an input register which supplies write commands to a dynamic stage register. A multiplexer couples the dynamic stage register and the input register to the command FIFO so that only the initial command of a single or multi-beat write burst is written to the command FIFO from the dynamic stage register. Consequently, separate write commands are not stored for each data beat, resulting in minimal areal size for the integrated circuit chip containing the command FIFO. Instead, a counter counts the number of beats in the multi-beat burst, so that when the last beat is received, the initial command and the beat count are supplied to the command FIFO. The device controller calculates the starting address of each subsequent data beat based on the prior beat address and the size of the data beat, to a limit established by the beat count. Non-queued read commands are transferred by the multiplexer directly from the input register to the command FIFO so that latency is not added to the processing of read commands.

US Patent:

6938113, Aug 30, 2005

Filed:

May 20, 2002

Appl. No.:

10/152265

Inventors:

Russell B. Stuber - Boulder CO, US
Robert W. Moss - Longmont CO, US
Alan R. Gilchrist - Danville CA, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F013/42

US Classification:

710110, 710 35, 709208

Abstract:

When a master device resets, flush commands are issued to a flush master register in the slave devices. A comparator compares the identification of the master device associated with the flush command to an identification of the master device associated with data for return by the slave device. A gate is responsive to the comparator to flush data from the data register that are pending for return.

US Patent:

6948019, Sep 20, 2005

Filed:

Apr 30, 2002

Appl. No.:

10/137459

Inventors:

Russell B. Stuber - Boulder CO, US
Robert W. Moss - Longmont CO, US
David O. Sluiter - Superior CO, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F012/00
G06F013/14
G06F013/38

US Classification:

710240, 710107, 710112, 710113, 710309, 710 36, 710311, 710241

Abstract:

A slave device on a data bus has a register that stores a non-queued split master vector containing bits identifying whether a transaction with corresponding master devices have been split. An input gate is responsive to the status of the slave device and to receipt of a command from a master device when the slave device status is busy to set a bit in the non-queued split master vector identifying that the transaction with the corresponding master device is split. An output gate is responsive to a not busy status of the slave device to output the non-queued split master vector to the arbiter to re-arbitrate use of the data bus among the previously-split non-queued master devices.

US Patent:

7065683, Jun 20, 2006

Filed:

Dec 5, 2001

Appl. No.:

10/011796

Inventors:

David O. Sluiter - Superior CO, US
Robert W. Moss - Longmont CO, US
Mark J. Kwong - Santa Clara CA, US
Peter Korger - Frederick CO, US
Christopher M. Giles - Lafayette CO, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11B 20/20
G06F 11/00

US Classification:

714700, 714744

Abstract:

An apparatus including a plurality of first base circuits, a plurality of second base circuits, a first test circuit, a second test circuit, and a test path. The plurality of first base circuits may be coupled to the plurality of second base circuits via one or more base circuit paths on a layout. The first test circuit may be disposed in a first distal location of the layout. The second test circuit may be disposed in a second distal location of the layout. The test path may be configured to (i) couple the first test circuit to the second test circuit and (ii) generate a test time delay from the first test circuit to the second test circuit incrementally longer than a maximum time delay generated by any of the base circuit paths.

US Patent:

7174401, Feb 6, 2007

Filed:

Feb 28, 2002

Appl. No.:

10/086786

Inventors:

Russell B. Stuber - Boulder CO, US
Robert W. Moss - Longmont CO, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 13/00

US Classification:

710110, 710113, 710118, 710240

Abstract:

A data bus transfers data between at least one slave device and a plurality of master devices, and an arbiter grants access to each of the master devices. The slave device includes look-ahead apparatus that includes staging register for staging an identification of a master device and a decoder for comparing a staged identification to an identification of a command from the bus. The look-ahead apparatus issues split releases of a next master device while the slave device returns data associated with a prior command.

US Patent:

63272075, Dec 4, 2001

Filed:

Apr 9, 2001

Appl. No.:

9/829377

Inventors:

David O. Sluiter - Boulder CO
Robert W. Moss - Longmont CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 700

US Classification:

365221

Abstract:

A digital logic circuit, such as a FIFO memory includes pointers, or indicators, generated in two clock domains, between which information is transferred, to indicate a location in the digital logic circuit for transferring the information into or out of the digital logic circuit within either clock domain. Each pointer is encoded with a "2-hot" encoded value within one of the clock domains. The 2-hot encoded value of each pointer is sent to the other clock domain to synchronize the pointer to the other clock domain as well as to its original clock domain. Within each clock domain, the pointer generated therein and the pointer received from the other clock domain are used to determine whether the information can be transferred into or out of the digital logic circuit.