Robert L Neff

US Patent:

20030146861, Aug 7, 2003

Filed:

Feb 1, 2002

Appl. No.:

10/061138

Inventors:

Kenneth Poulton - Palo Alto CA, US
Robert Neff - Palo Alto CA, US
Matthew Holcomb - Colorado Springs CO, US
James Kang - Monmouth Junction NJ, US

International Classification:

H03M001/10

US Classification:

341/120000

Abstract:

A method of calibrating a high-speed analog to digital converter and an ADC that implements the method. Multiple linear regression analysis is used to calibrate the stages of a pipeline ADC to compensate for variations in gain from stage to stage and optionally to compensate for harmonic distortion. Current amplifiers each having gain of about 1.6 are used for low power consumption, minimal surface area requirements, and rapid sampling speed. Weighting factors are stored in lookup tables to minimize the number of adders required to generate the output digital word.

US Patent:

20030151441, Aug 14, 2003

Filed:

Feb 1, 2002

Appl. No.:

10/061504

Inventors:

Robert Neff - Palo Alto CA, US

International Classification:

G06F001/04

US Classification:

327/295000

Abstract:

The interleaved clock generator generates N interleaved clock signals in response to an input clock signal. The interleaved clock generator comprises an interleaved clock generator of a first type for receiving the input clock signal and for generating M interleaved intermediate clock signals in response to the input clock signal. The interleaved clock generator of the first type includes either a multi-stage serial-delay circuit or a ring counter circuit. The interleaved clock generator additionally comprises M interleaved clock generators of a second type, each of which is each for receiving a respective one of the intermediate clock signals from the clock generator of the first type and for generating N/M of the N interleaved clock signals in response to the respective one of the intermediate clock signals. Each of the interleaved clock generators of the second type includes either a ring counter circuit or a multi-stage serial-delay circuit: a ring counter when the interleaved clock generator of the first type includes a multi-stage serial-delay circuit; a multi-stage serial-delay circuit when the interleaved clock generator of the first type includes a ring counter circuit.

US Patent:

20040150432, Aug 5, 2004

Filed:

Jan 30, 2003

Appl. No.:

10/354281

Inventors:

Kenneth Poulton - Palo Alto CA, US
Robert Neff - Palo Alto CA, US
Jorge Pernillo - Daly City CA, US
Mehrdad Heshami - Palo Alto CA, US

International Classification:

H03B001/00
H03K003/00

US Classification:

327/108000

Abstract:

A line driver fabricated from CMOS devices that provides a substantially constant output impedance over a significant range of a time-varying input voltage includes a time-varying current source, a pair of CMOS output loads, and a pair of biasing circuits. Each CMOS output load includes a NMOS transistor and a PMOS transistor connected in parallel and each biased into a linear range of operation. In response to a time-varying input voltage, the time-varying current source draws current from the pair of CMOS output loads in a manner that operates each CMOS output load to collectively establish a time-varying output voltage component at an associated output terminal.

US Patent:

20050007160, Jan 13, 2005

Filed:

Jul 10, 2003

Appl. No.:

10/616794

Inventors:

Robert Neff - Palo Alto CA, US

International Classification:

H02M011/00
H03D001/00
H01L021/8238

US Classification:

327103000

Abstract:

The tunable differential transconductor includes a tail current sink and a differentially-connected pair of FETs connected to the tail current source. At least one of the FETs is a composite FET that includes a main FET connected in parallel with a switchable tuning element. The switchable tuning element is operable to change an effective channel dimension, i.e., at least one of effective channel length and effective channel width, of the composite FET. In the method, a differential transconductor that includes a tail current sink and a differentially-connected pair of composite FETs connected to the tail current sink is provided. The effective channel dimension of at least one of the composite FETs is changed to establish one or more of a desired transconductance, a desired transconductance linearity and a desired offset of the differential transconductor.

US Patent:

20050047512, Mar 3, 2005

Filed:

Aug 28, 2003

Appl. No.:

10/650862

Inventors:

Robert Neff - Palo Alto CA, US
Robert Jewett - Redwood City CA, US

International Classification:

H04L027/00

US Classification:

375259000

Abstract:

Advantage is taken of self-synchronized scrambler techniques to randomize data transitions across an interface thereby reducing the likelihood of interference induced by legitimate data changes in the data system. This arrangement reduces cross-talk in electronic circuits which results from coherent interference.

US Patent:

20050078016, Apr 14, 2005

Filed:

Oct 14, 2003

Appl. No.:

10/684992

Inventors:

Robert Neff - Palo Alto CA, US

International Classification:

H03M007/00

US Classification:

341050000

Abstract:

A source signal is provided. The source signal is XORed with a scrambling random signal to generate a scrambled signal. The scrambled signal is transmitted through the digital logic circuit. The scrambled signal is XORed with the descrambling random signal logically identical to the scrambling random signal to produce a descrambled signal identical to the source signal. In one embodiment, the scrambling random signal is transmitted through the digital logic circuit and used as the descrambling random signal. In another embodiment, the scrambling random signal and descrambling random signal are generated independently using pseudo-random number generators. In yet another embodiment, the scrambling random signal is self-synchronizing and is contained within the pattern of the scrambled signal.

US Patent:

20060250288, Nov 9, 2006

Filed:

May 3, 2005

Appl. No.:

11/120698

Inventors:

Andrew Fernandez - Palo Alto CA, US
Vamsi Srikantam - Palo Alto CA, US
Robert Neff - Palo Alto CA, US
Kenneth Poulton - Palo Alto CA, US

International Classification:

H03M 1/10

US Classification:

341120000

Abstract:

A method for calibrating time interleaved samplers comprising applying a calibration signal to a time-interleaved sampling device, wherein the signal is coherent with at least one sample clock on the device and is periodic and has a predetermined spectral content and frequency, sampling, by said time-interleaved sampling device, the calibration signal at a plurality of phases to form samples, averaging the formed samples, and calculating the phase error of each sample based on the average calibration signal sample.

US Patent:

20070002893, Jan 4, 2007

Filed:

Jul 1, 2005

Appl. No.:

11/173134

Inventors:

Robert Neff - Palo Alto CA, US
Kenneth Poulton - Palo Alto CA, US
Brian Setterberg - Menlo Park CA, US
Bernd Wuppermann - Pacifica CA, US
Scott Genther - Colorado Springs CO, US
Allen Montijo - Colorado Springs CO, US

International Classification:

H04J 3/22

US Classification:

370465000

Abstract:

An I/O interface provides multiple serial data lines each with an embedded clock to provide sufficient data handling capacity to accommodate high data rates that are associated with high-speed data converters.