Robert D Proctor

US Patent:

6499134, Dec 24, 2002

Filed:

Jul 13, 2000

Appl. No.:

09/615149

Inventors:

Patrick H. Buffet - Essex Junction VT
Paul E. Dunn - Fletcher VT
Joseph Natonio - Poughkeepsie NY
Robert A. Proctor - South Burlington VT
Gulsun Yasar - South Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1750

US Classification:

716 12, 716 13, 716 14, 716 15

Abstract:

A method for improving the crosstalk and time-of-flight performance for signals in an integrated circuit with respect to the package-related wiring. I/O pads in the package-related wiring of a logic design meeting specified crosstalk and time-of-flight constraints are identified using a software tool. The tool produces a graphical display in which the identified I/O pads are highlighted. The tool enables a user to graphically manipulate the display to assign, i. e. , establish an electrical connection, between I/O circuits corresponding to the signals and the highlighted I/O pads.

US Patent:

6584606, Jun 24, 2003

Filed:

Jun 1, 2000

Appl. No.:

09/584416

Inventors:

Charles S. Chiu - Essex Junction VT
James P. Libous - Endwell NY
Rory D. Loughran - Richmond VT
Joseph Natonio - Poughkeepsie NY
Robert A. Proctor - South Burlington VT
Gulsun Yasar - South Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1750

US Classification:

716 10, 716 4, 716 8

Abstract:

A method of analyzing I/O cell layouts for integrated circuits, such as ASICs, includes defining a proposed I/O cell layout on a selected chip image, providing a set of limit rules for electromigration, IR voltage drop and di/dt noise for the selected chip image, providing characteristics for each I/O cell type used in the proposed I/O cell layout, checking the proposed I/O cell layout by applying the limit rules to the proposed I/O cell layout and reporting all I/O cells used in the proposed I/O cell layout that do not meet the limit rules for the selected chip image.

US Patent:

6868374, Mar 15, 2005

Filed:

Oct 3, 2000

Appl. No.:

09/677913

Inventors:

Gary S. Ditlow - Garrison NY, US
Robert A. Proctor - South Burlington VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F017/50
G06G007/54

US Classification:

703 18, 703 22, 716 4, 716 17

Abstract:

A method and system for testing the compliance of a distribution of I/O circuits in a semiconductor chip with voltage (IR) and electromigration (EM) limits. Maximum and average currents for the I/O circuits are calculated. A resistance model for the power distribution network of the chip is created, and the I/O circuit currents are indexed to corresponding nodes in the resistance model. Average current demand of the logic circuitry of the chip is also calculated and indexed to nodes in the resistance model. The resistance model with indexed currents is then solved to determine voltages at the nodes. The voltages are checked for compliance with IR and EM limits, and a report is produced. If violations of the IR and EM limits are detected, the placement of the I/O circuits in the power distribution network may be revised to bring the design into compliance with IR and EM requirements.

US Patent:

7065728, Jun 20, 2006

Filed:

Sep 29, 2004

Appl. No.:

10/711633

Inventors:

Lu'ay Bakir - Bolton Valley VT, US
Ciaran J. Brennan - Essex Junction VT, US
Joseph N. Kozhaya - Essex Junction VT, US
Robert A. Proctor - South Burlington VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 8, 716 2, 716 9, 716 10

Abstract:

A method for placing electrostatic discharge clamps within integrated circuit devices is disclosed. A region is initially defined within an integrated circuit design. A list of ESD-susceptible circuits located within the defined region is then generated. The center of gravity of the ESD-susceptible circuits located within the defined region is located. Next, an ESD protection device is placed at the center of gravity of the ESD-susceptible circuits located within the defined region. A determination is made as to whether or not all ESD-susceptible circuits within the list of ESD-susceptible circuits are protected by the placement of the ESD protection device. If so, the process is repeated in other regions until the entire integrated circuit is addressed. Otherwise, the defined region is divided into at least two smaller regions and the process is repeated.