Robert P Reese

US Patent:

58676945, Feb 2, 1999

Filed:

Oct 7, 1996

Appl. No.:

8/723439

Inventors:

Richard Vincent Billings - Plano TX
George McNell Lattimore - Austin TX
Robert James Reese - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 106

US Classification:

395556

Abstract:

An information handling system, having a programmable clocking system for clocking data in and out of a processor, includes a processor, having one or more buses connected thereto, wherein a processor clock, and a clock for each of the buses connected to the processor, may be operating at different clock rates relative to each other, the programmable clocking circuit for generating bus clock signals with predetermined cycle skew eliminates the need to distribute separate clock signals across the processor chip. The clock generation circuit uses signals available on the processor integrated circuit for functional operation and tests. Further, flush and hold signals control predetermined latches in the clock generator circuit.