Robert B Reese

US Patent:

7246332, Jul 17, 2007

Filed:

Feb 8, 2005

Appl. No.:

11/053078

Inventors:

Joseph David Mendenhall - Cary NC, US
John Christopher Morris - Durham NC, US
Robert James Reese - Austin TX, US
Chad Everett Winemiller - Cary NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 4, 716 5, 703 13

Abstract:

Methods, systems, and media for functional simulation of an I/O bus are disclosed. More particularly, a method of simulating distortion and noise parameters of an I/O bus is disclosed. Embodiments include constraining one or more fields of a record and determining delay amounts based on the resulting parameters, where the final delay amount includes a delay buffer and a net of delay amounts associated with the parameters. Embodiments may also include determining a value of a next bit to be sent to the I/O bus and, after waiting the delay amount, driving the bit on the bus to the next bit value. Parameters may include skew, jitter, duty cycle distortion, voltage reference distortion, and drift of any of these parameters. Further embodiments may include signaling the end of a phase in response to a phase done condition being satisfied.

US Patent:

20060182187, Aug 17, 2006

Filed:

Feb 11, 2005

Appl. No.:

11/055807

Inventors:

Robert Likovich - Raleigh NC, US
Robert Reese - Austin TX, US
Joseph Mendenhall - Cary NC, US
Kenneth Barker - Holly Springs NC, US

International Classification:

H04B 3/00

US Classification:

375257000

Abstract:

A test pattern is loaded into a driver data shift register and sent from a driver chip to a receive chip over an M bit bus (0 to M−1). The test pattern is also generated at the receiver chip and used to compare to the actual received data. Failed compares are stored as logic ones in a bit error register (BER). A counter determines the number of failures by counting logic ones from the BER. The contents of a error position counter are latched in a error position latch and used to load a logic one (at the error bit position) into daisy chained self-heal control registers (SCR) in the receiver chip and the driver chip. The SCR sets a logic one into all bit positions after the error bit isolating the failed bit path and adding a spare bit path which is in bit position M.

US Patent:

20080162998, Jul 3, 2008

Filed:

Mar 14, 2008

Appl. No.:

12/048284

Inventors:

Robert B. Likovich - Raleigh NC, US
Robert J. Reese - Austin TX, US
Joseph D. Mendenhall - Cary NC, US
Kenneth J. Barker - Holly Springs NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00

US Classification:

714 28, 714E11001

Abstract:

A test pattern is loaded into a driver data shift register and sent from a driver chip to a receive chip over an M bit bus ( to M−1). The test pattern is also generated at the receiver chip and used to compare to the actual received data. Failed compares are stored as logic ones in a bit error register (BER). A counter determines the number of failures by counting logic ones from the BER. The contents of a error position counter are latched in a error position latch and used to load a logic one (at the error bit position) into daisy chained self-heal control registers (SCR) in the receiver chip and the driver chip. The SCR sets a logic one into all bit positions after the error bit isolating the failed bit path and adding a spare bit path which is in bit position M.