Robert J Robison

US Patent:

7709926, May 4, 2010

Filed:

Apr 24, 2008

Appl. No.:

12/108924

Inventors:

Wagdi W. Abadeer - Jericho VT, US
Kiran V. Chatty - Williston VT, US
Robert J. Gauthier - Hinesburg VT, US
Jed H. Rankin - Richmond VT, US
Robert R. Robison - Colchester VT, US
William R. Tonti - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/06

US Classification:

257510, 257506, 257509, 257513, 257E29019, 257E2902

Abstract:

Device structure for active devices fabricated in a semiconductor-on-insulator (SOI) substrate and design structures for a radiofrequency integrated circuit. The device structure includes a first isolation region in the semiconductor layer that extends from a top surface of a semiconductor layer to a first depth, a second isolation region in the semiconductor layer that extends from the top surface of the semiconductor layer to a second depth greater than the first depth, and a first doped region in the semiconductor layer. The first doped region is disposed vertically between the first isolation region and an insulating layer disposed between the semiconductor layer and a handle wafer of the SOI substrate. The device structure may be included in a design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit.

US Patent:

7737498, Jun 15, 2010

Filed:

May 7, 2008

Appl. No.:

12/116237

Inventors:

Kiran V. Chatty - Williston VT, US
Jed Hickory Rankin - Richmond VT, US
Robert R. Robison - Colchester VT, US
William Robert Tonti - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/00
H01L 21/338

US Classification:

257347, 438151, 257E21424

Abstract:

Field effect transistor and methods of fabricating field effect transistors. The field effect transistors includes: a semiconductor substrate; a silicon oxide layer on the substrate; a stiffening layer on the silicon oxide layer; a single crystal silicon layer on the stiffening layer; a source and a drain on opposite sides of a channel region of the silicon layer; a gate electrode over the channel region and a gate dielectric between the gate electrode and the channel region.

US Patent:

7790564, Sep 7, 2010

Filed:

Apr 24, 2008

Appl. No.:

12/108851

Inventors:

Wagdi W. Abadeer - Jericho VT, US
Kiran V. Chatty - Williston VT, US
Jed H. Rankin - Richmond VT, US
Robert R. Robison - Colchester VT, US
William R. Tonti - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/331
H01L 21/76
H01L 21/22
H01L 21/38
H01L 21/762

US Classification:

438361, 438427, 438549, 257511, 257552, 257E21382, 257E21545, 257E21551, 257E21564

Abstract:

Methods for fabricating a device structure in a semiconductor-on-insulator substrate. The method includes forming a first isolation region in the substrate device layer that extends from a top surface of the device layer to a first depth and forming a second isolation region in the semiconductor layer that extends from the top surface of the semiconductor layer to a second depth greater than the first depth. The method further includes forming a doped region of the device structure in the semiconductor layer that is located vertically between the first isolation region and the insulating layer.

US Patent:

7808039, Oct 5, 2010

Filed:

Apr 9, 2008

Appl. No.:

12/099879

Inventors:

Jin Cai - Cortlandt Manor NY, US
Jeffrey B. Johnson - Essex Junction VT, US
Tak H. Ning - Yorktown Heights NY, US
Robert R. Robison - Colchester VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27/088

US Classification:

257328, 257367, 257406, 438209, 438328

Abstract:

A semiconductor-on-insulator transistor device includes a source region, a drain region, a body region, and a source-side lateral bipolar transistor. The source region has a first conductivity type. The body region has a second conductivity type and is positioned between the source region and the drain region. The source-side lateral bipolar transistor includes a base, a collector, and an emitter. A silicide region connects the base to the collector. The emitter is the body region. The collector has the second conductivity type, and the base is the source region and is positioned between the emitter and the collector.

US Patent:

7855110, Dec 21, 2010

Filed:

Jul 8, 2008

Appl. No.:

12/169118

Inventors:

Viorel Ontalus - Danbury CT, US
Robert Robison - Colchester VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/336

US Classification:

438197, 438305, 438306, 257E21433

Abstract:

An FET and method of fabricating an FET. The method includes forming a gate dielectric layer on a top surface of a silicon region of a substrate and forming a gate electrode on a top surface of the gate dielectric layer; forming a source and a drain in the silicon region and separated by a channel region under the gate electrode, the source having a source extension extending under the gate electrode and the drain having a drain extension extending under the gate electrode, the source, source extension, drain and drain extension doped a first type; and forming a source delta region contained entirely within the source and forming a drain delta region contained entirely within the drain, the delta source region and the delta drain region doped a second dopant type, the second dopant type opposite from the first dopant type.

US Patent:

7888266, Feb 15, 2011

Filed:

Jun 26, 2008

Appl. No.:

12/146560

Inventors:

Kangguo Cheng - Guilderland NY, US
Toshiharu Furukawa - Essex Junction VT, US
Robert Robison - Colchester VT, US
William R. Tonti - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/311

US Classification:

438700, 438199, 438508, 438 70, 257E21051, 257E21054, 257E21058, 257E21085, 257E21092, 257E21126, 257E21127, 257E21231, 257E21267, 257E2132, 257E21304, 257E21435, 257E27133, 257E27134

Abstract:

A complementary metal-oxide-semiconductor (CMOS) optical sensor structure includes a pixel containing a charge collection well of a same semiconductor material as a semiconductor layer in a semiconductor substrate and at least another pixel containing another charge collection well of a different semiconductor material than the material of the semiconductor layer. The charge collections wells have different band gaps, and consequently, generate charge carriers in response to light having different wavelengths. The CMOS sensor structure thus includes at least two pixels responding to light of different wavelengths, enabling wavelength-sensitive, or color-sensitive, capture of an optical data.

US Patent:

7936017, May 3, 2011

Filed:

May 15, 2008

Appl. No.:

12/120836

Inventors:

Toshiharu Furukawa - Essex Junction VT, US
Xuefeng Hua - Guilderland NY, US
Robert R. Robison - Colchester VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27/01
H01L 27/12
H01L 31/0392

US Classification:

257347, 257192, 438530

Abstract:

A method, gated device and design structure are presented for providing reduced floating body effect (FBE) while not impacting performance enhancing stress. One method includes forming damage in a portion of a substrate adjacent to a gate; removing a portion of the damaged portion to form a trench, leaving another portion of the damaged portion at least adjacent to a channel region; and substantially filling the trench with a material to form a source/drain region.

US Patent:

7939911, May 10, 2011

Filed:

Aug 14, 2008

Appl. No.:

12/191683

Inventors:

Wagdi W. Abadeer - Jericho VT, US
Kiran V. Chatty - Williston VT, US
Jed H. Rankin - Richmond VT, US
Robert Robison - Colchester VT, US
Yun Shi - South Burlington VT, US
William R. Tonti - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/00

US Classification:

257538, 257E21004, 257E29001

Abstract:

In one embodiment, a back-end-of-line (BEOL) resistive structure comprises a second metal line embedded in a second dielectric layer and overlying a first metal line embedded in a first dielectric layer. A doped semiconductor spacer or plug laterally abutting sidewalls of the second metal line and vertically abutting a top surface of the first metal line provides a resistive link between the first and second metal lines. In another embodiment, another BEOL resistive structure comprises a first metal line and a second metal line are embedded in a dielectric layer. A doped semiconductor spacer or plug laterally abutting the sidewalls of the first and second metal lines provides a resistive link between the first and second metal lines.