Robert L Robison

US Patent:

7808039, Oct 5, 2010

Filed:

Apr 9, 2008

Appl. No.:

12/099879

Inventors:

Jin Cai - Cortlandt Manor NY, US
Jeffrey B. Johnson - Essex Junction VT, US
Tak H. Ning - Yorktown Heights NY, US
Robert R. Robison - Colchester VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27/088

US Classification:

257328, 257367, 257406, 438209, 438328

Abstract:

A semiconductor-on-insulator transistor device includes a source region, a drain region, a body region, and a source-side lateral bipolar transistor. The source region has a first conductivity type. The body region has a second conductivity type and is positioned between the source region and the drain region. The source-side lateral bipolar transistor includes a base, a collector, and an emitter. A silicide region connects the base to the collector. The emitter is the body region. The collector has the second conductivity type, and the base is the source region and is positioned between the emitter and the collector.

US Patent:

8361872, Jan 29, 2013

Filed:

Sep 7, 2010

Appl. No.:

12/876480

Inventors:

Jin Cai - Cortlandt Manor NY, US
Toshiharu Furukawa - Essex Junction VT, US
Robert R. Robison - Colchester VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/336
H01L 29/02

US Classification:

438303, 438289, 438290, 438197, 438301, 257408

Abstract:

A method of forming a semiconductor device includes: forming a channel of a field effect transistor (FET) in a substrate; forming a heavily doped region in the substrate; and forming recesses adjacent the channel and the heavily doped region. The method also includes: forming an undoped or lightly doped intermediate layer in the recesses on exposed portions of the channel and the heavily doped region; and forming source and drain regions on the intermediate layer such that the source and drain regions are spaced apart from the heavily doped region by the intermediate layer.

US Patent:

20130113051, May 9, 2013

Filed:

Jan 2, 2013

Appl. No.:

13/732636

Inventors:

International Business Machenes Corporation - Armonk NY, US
Toshiharu Furukawa - Essex Junction VT, US
Robert R. Robison - Colchester VT, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 29/78

US Classification:

257402

Abstract:

A method of forming a semiconductor device includes: forming a channel of a field effect transistor (FET) in a substrate; forming a heavily doped region in the substrate; and forming recesses adjacent the channel and the heavily doped region. The method also includes: forming an undoped or lightly doped intermediate layer in the recesses on exposed portions of the channel and the heavily doped region; and forming source and drain regions on the intermediate layer such that the source and drain regions are spaced apart from the heavily doped region by the intermediate layer.

US Patent:

20130200434, Aug 8, 2013

Filed:

Mar 13, 2013

Appl. No.:

13/798643

Inventors:

International Business Machines Corporation - Armonk NY, US
Jeffrey P. Gambino - Westford VT, US
Kirk D. Peterson - Jericho VT, US
Jed H. Rankin - Richmond VT, US
Robert R. Robison - Colchester VT, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 27/092

US Classification:

257192, 257369

Abstract:

Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET.

US Patent:

20130200486, Aug 8, 2013

Filed:

Mar 15, 2013

Appl. No.:

13/835463

Inventors:

International Business Machines Corporation - Armonk NY, US
Jason E. Cummings - Albany NY, US
Toshiharu Furukawa - Essex Junction VT, US
Robert J. Gauthier - Hinesburg VT, US
Jed H. Rankin - Richmond VT, US
Robert R. Robison - Colchester VT, US
William R. Tonti - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/06

US Classification:

257507

Abstract:

Various aspects include extremely thin semiconductor-on-insulator (ETSOI) layers. In one embodiment, an ETSOI layer includes a plurality of shallow trench isolations (STI) defining a plurality of distinct semiconductor-on-insulator (SOI) regions, the distinct SOI regions having at least three different thicknesses; at least one recess located within the distinct SOI regions; and an oxide cap over the at least one recess.