Dr. Robison graduated from the Indiana University School of Medicine in 1979. He works in Indianapolis, IN and specializes in Congenital Cardiac Surgery (Thoracic Surgery). Dr. Robison is affiliated with St Vincent Carmel Hospital and St Vincent Indianapolis Hospital & Heart Center.
Kangguo Cheng - Guilderland NY, US Toshiharu Furukawa - Essex Junction VT, US Robert Robison - Colchester VT, US William R. Tonti - Essex Junction VT, US
Assignee:
International Business Machines Corporation - Armonk NY
A complementary metal-oxide-semiconductor (CMOS) optical sensor structure includes a pixel containing a charge collection well of a same semiconductor material as a semiconductor layer in a semiconductor substrate and at least another pixel containing another charge collection well of a different semiconductor material than the material of the semiconductor layer. The charge collections wells have different band gaps, and consequently, generate charge carriers in response to light having different wavelengths. The CMOS sensor structure thus includes at least two pixels responding to light of different wavelengths, enabling wavelength-sensitive, or color-sensitive, capture of an optical data.
Kangguo Cheng - Guilderland NY, US Toshiharu Furukawa - Essex Junction VT, US Robert R. Robison - Colchester VT, US William R. Tonti - Essex Junction VT, US Richard Q. Williams - Essex Junction VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 31/105
US Classification:
257458, 257E31061
Abstract:
A diode comprises a substrate formed of a first material having a first doping polarity. The substrate has a planar surface and at least one semispherical structure extending from the planar surface. The semispherical structure is formed of the first material. A layer of second material is over the semispherical structure. The second material comprises a second doping polarity opposite the first doping polarity. The layer of second material conforms to the shape of the semispherical structure. A first electrical contact is connected to the substrate, and a second electrical contact is connected to the layer of second material. Additional semiconductor structures are formed by fabricating additional layers over the original layers.
Kangguo Cheng - Guilderland NY, US Toshiharu Furukawa - Essex Junction VT, US Robert Robison - Colchester VT, US William R. Tonti - Essex Junction VT, US
Assignee:
International Business Machines Corporation - Armonk NY
A complementary metal-oxide-semiconductor (CMOS) optical sensor structure comprises a pixel containing a charge collection well of a same semiconductor material as a semiconductor layer in a semiconductor substrate and at least another pixel containing another charge collection well of a different semiconductor material than the material of the semiconductor layer. The charge collections wells have different band gaps, and consequently, generate charge carriers in response to light having different wavelengths. The CMOS sensor structure thus includes at least two pixels responding to light of different wavelengths, enabling wavelength-sensitive, or color-sensitive, capture of an optical data. Further, a design structure for the inventive complementary metal-oxide-semiconductor (CMOS) image sensor is also provided.
Creating Extremely Thin Semiconductor-On-Insulator (Etsoi) Having Substantially Uniform Thickness
Nathaniel C. Berliner - Albany NY, US Kangguo Cheng - Albany NY, US Jason E. Cummings - Albany NY, US Toshiharu Furukawa - Essex Junction VT, US Jed H. Rankin - Essex Junction VT, US Robert R. Robison - Essex Junction VT, US William R. Tonti - Essex Junction VT, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
H01L 29/06 H01L 21/66 C23F 1/08
US Classification:
257506, 438 16, 15634513, 257E21529, 257E29006
Abstract:
An extremely thin semiconductor-on-insulator (ETSOI) wafer is created having a substantially uniform thickness by measuring a semiconductor layer thickness at a plurality of selected points on a wafer; determining a removal thickness to be removed at each of the plurality of selected points such that removal of the removal thickness results in a substantially uniform within-wafer semiconductor layer thickness; implanting a species into the wafer at each of the plurality of selected points with at least one of a dose level and an energy level based on the removal thickness for the respective point; and polishing the semiconductor layer to thin the semiconductor layer.
- Armonk NY, US Lawrence A. Clevenger - Saratoga Springs NY, US Christopher J. Penny - Saratoga Springs NY, US Kisik Choi - Watervliet NY, US Nicholas Anthony Lanzillo - Wynantskill NY, US Robert Robison - Rexford NY, US
International Classification:
H01L 23/528 H01L 21/768
Abstract:
Integrated chips include first lines, formed on an underlying substrate. Spacers are formed conformally on sidewalls of the plurality of lines. Etch stop remnants are positioned on the sidewalls of the plurality of lines, between the spacers and the underlying substrate. Second lines are formed on the underlying substrate, between respective pairs of adjacent first lines.
- Armonk NY, US Lawrence A. Clevenger - Saratoga Springs NY, US Kisik Choi - Watervliet NY, US Nicholas Anthony Lanzillo - Wynantskill NY, US Christopher J. Penny - Saratoga Springs NY, US Robert Robison - Rexford NY, US
International Classification:
H01L 21/768 H01L 21/02 H01L 21/04 H01L 21/3105
Abstract:
A method for fabricating a semiconductor device including a self-aligned top via includes subtractively etching a conductive layer to form at least a first conductive line on a substrate. After the subtractive etching, the method further includes forming a barrier layer along the substate and along the first conductive line, planarizing at least portions of the barrier layer to obtain at least an exposed first conductive line, recessing at least the exposed first conductive line to form a first recessed conductive line, and forming conductive material in a via opening on the first recessed conductive line.
- Armonk NY, US Somnath Ghosh - Clifton Park NY, US Lawrence A. Clevenger - Saratoga Springs NY, US Robert Robison - Rexford NY, US
International Classification:
H01L 23/522 H01L 23/528 H01L 23/532
Abstract:
An interlayer interconnect for an integrated circuit includes a first line in a first wiring layer, a first via portion integral to and extending from the first line, and a second line in a second wiring layer that is adjacent to the first wiring layer. The interlayer interconnect also includes a third line in the second wiring layer that is a first distance from the second line, wherein the first distance is a pitch of the second wiring layer, and a second via portion integral to and extending from the second line and in electrical contact with the first via portion at an interface to form a via. The via extends a second distance that is at least one-and-a-quarter times the pitch.
- Armonk NY, US Lawrence A. Clevenger - Saratoga Springs NY, US Kisik Choi - Watervliet NY, US Nicholas Anthony Lanzillo - Wynantskill NY, US Christopher J. Penny - Saratoga Springs NY, US Robert Robison - Rexford NY, US
International Classification:
H01L 23/522 H01L 21/768 H01L 23/528 H01L 21/311
Abstract:
Integrated chips include a dielectric layer that includes at least one trench and at least one plug region. A line is formed in the dielectric layer in the at least one trench and terminates at the plug region. A dielectric plug is formed in the plug region.
Normandy Elementary School Littleton CO 1972-1979, Euclid Middle School Littleton CO 1979-1981, John Wesley Powell Middle School Littleton CO 1981-1981