Robert M Ruth

US Patent:

20120306045, Dec 6, 2012

Filed:

Jun 1, 2011

Appl. No.:

13/150924

Inventors:

Robert S. Ruth - Austin TX, US
Mark A. Kearney - Austin TX, US
Bernard J. Pappert - Austin TX, US
Juxiang Ren - Austin TX, US
Jeff L. Warner - Austin TX, US

International Classification:

H01L 21/762
H01L 29/34
G06F 17/50

US Classification:

257499, 438433, 716123, 257E21546, 257E29108

Abstract:

A semiconductor device includes CMP dummy tiles () that are converted to active tiles by forming well regions () at a top surface of the dummy tiles, forming silicide () on top of the well regions, and forming a metal interconnect structure () in contact with the silicided well tie regions for electrically connecting the dummy tiles to a predetermined supply voltage to provide latch-up protection.

US Patent:

20170063371, Mar 2, 2017

Filed:

Aug 26, 2015

Appl. No.:

14/836223

Inventors:

- AUSTIN TX, US
STEFANO PIETRI - AUSTIN TX, US
JUXIANG REN - AUSTIN TX, US
ROBERT S. RUTH - AUSTIN TX, US

International Classification:

H03K 17/687

Abstract:

A substrate bias circuit and method for biasing a substrate are provided. A substrate bias circuit includes a first voltage source, a second voltage source, a diode coupled between the first voltage source and the second voltage source, and a plurality of transistors, each transistor in the plurality of transistors having a substrate terminal. In one example, the first voltage source supplies, via the diode, the substrate terminal of a first transistor of the plurality of transistors during a power-up, and the second voltage source supplies the substrate terminal of the first transistor after the power-up.

US Patent:

20160126729, May 5, 2016

Filed:

Oct 31, 2014

Appl. No.:

14/529282

Inventors:

- AUSTIN TX, US
MELANIE ETHERTON - AUSTIN TX, US
JAMES W. MILLER - AUSTIN TX, US
MOHAMED S. MOUSA - AUSTIN TX, US
ROBERT S. RUTH - AUSTIN TX, US
MICHAEL A. STOCKINGER - AUSTIN TX, US

International Classification:

H02H 9/04

Abstract:

An integrated circuit including ESD circuitry that is shared among more than one terminal segment of the integrated circuit to discharge current from an ESD event on any of the terminal segments. The shared ESD circuitry includes a clamp circuit that is coupled to power buses of each segment to discharge current from ESD events on each segment. The shared ESD circuitry includes a trigger circuit that is coupled to nodes coupled to terminals of each segment to detect an ESD event on each segment.

US Patent:

20150349522, Dec 3, 2015

Filed:

May 28, 2014

Appl. No.:

14/289083

Inventors:

James W. Miller - Austin TX, US
Melanie Etherton - Austin TX, US
Alex P. Gerdemann - Austin TX, US
Mohamed S. Moosa - Austin TX, US
Jonathan M. Phillippe - Austin TX, US
Robert S. Ruth - Austin TX, US

International Classification:

H02H 9/04

Abstract:

An integrated circuit includes a plurality of I/O cells, each including a portion of the first power bus, a portion of the second power bus, and an I/O pad coupled between the portions of the first and second power buses. A first set of the plurality of I/O cells is arranged along a die edge of the integrated circuit. A second set of the plurality of I/O cells is arranged along the die edge between the first set and the die edge. For each I/O cell in the first set, the portion of the first power bus is physically connected to the portion of the first power bus of an abutting I/O cell of the second set at a boundary between the I/O cell of the first set and the abutting I/O cell of the second set. The integrated circuit includes an ESD clamp and a trigger circuit.

US Patent:

20140380258, Dec 25, 2014

Filed:

Feb 23, 2012

Appl. No.:

14/380384

Inventors:

Xavier Hours - Tournefeuille, FR
Shitiz Arora - Noida, IN
Robert Scott Ruth - Austin TX, US

Assignee:

Freescale Semiconductor, Inc - Austin TX

International Classification:

G06F 17/50

US Classification:

716112

Abstract:

A method of performing layout verification for an integrated circuit (IC) layout is described. The method comprises receiving layout information for the IC layout, identifying at least one IC component within the IC layout, extracting localised layout information for the at least one IC component from the received layout information, defining the localised layout information for the at least one IC component within at least one component instance parameter therefor, and performing at least one layout verification check for the at least one component based at least partly on the at least one component instance parameter.

US Patent:

20140353727, Dec 4, 2014

Filed:

May 30, 2013

Appl. No.:

13/905275

Inventors:

MELANIE ETHERTON - Austin TX, US
ALEXEY GILBUR - Holon, IL
JAMES W. MILLER - Austin TX, US
JONATHAN M. PHILLIPPE - Austin TX, US
ROBERT S. RUTH - Austin TX, US

International Classification:

H01L 21/768
H01L 23/535

US Classification:

257203, 438129

Abstract:

An integrated circuit including an ESD network including a portion located in ESD subareas of a plurality of I/O cells where the ESD subareas are arranged in a row traversing the plurality of I/O cells. The ESD network includes ESD clamp cells and ESD trigger circuit cells wherein a portion of the network is located in the row. In some examples, the row includes an ESD trigger circuit cell with a portion in one subarea of one ESD subarea of one I/O cell and a second portion in a second ESD subarea of another I/O cell. Also described herein is a method for producing an integrated circuit layout with an ESD network.

US Patent:

20140327079, Nov 6, 2014

Filed:

May 2, 2013

Appl. No.:

13/875618

Inventors:

- Austin TX, US
Alex P. Gerdemann - Austin TX, US
James W. Miller - Austin TX, US
Mohamed S. Moosa - Round Rock TX, US
Robert S. Ruth - Austin TX, US
Michael A. Stockinger - Austin TX, US

International Classification:

H01L 27/02

US Classification:

257355

Abstract:

Boosted Electrostatic Discharge (ESD) clamp circuit with high effective holding voltage. In some embodiments, an integrated circuit may include a trigger circuit operably coupled to a first voltage bus and to a reference bus; a diode including an anode terminal operably coupled to a second voltage bus, the second voltage bus distinct from the first voltage bus; a transistor including a gate operably coupled to an output terminal of the trigger circuit, a drain operably coupled to a cathode terminal of the diode, and a source operably coupled to the reference bus; and an input/output (I/O) cell operably coupled to the first voltage bus, the second voltage bus, and the reference bus.

US Patent:

20140264728, Sep 18, 2014

Filed:

May 29, 2014

Appl. No.:

14/289730

Inventors:

Robert S. Ruth - Austin TX, US
Mark A. Kearney - Austin TX, US
Bernard J. Pappert - Austin TX, US
Juxiang Ren - Austin TX, US
Jeff L. Warner - Austin TX, US

Assignee:

FREESCALE SEMICONDUCTOR, INC. - Austin TX

International Classification:

H01L 29/06
H01L 23/00
H01L 27/092

US Classification:

257517, 257519

Abstract:

A semiconductor device includes CMP dummy tiles () that are converted to active tiles by forming well regions () at a top surface of the dummy tiles, forming silicide () on top of the well regions, and forming, a metal interconnect structure () in contact with the silicided well tie regions for electrically connecting the dummy tiles to a predetermined supply voltage to provide latch-up protection.