Robert Leon Sadler

US Patent:

55656960, Oct 15, 1996

Filed:

Nov 21, 1995

Appl. No.:

8/561550

Inventors:

Dain C. Miller - Roanoke VA
Robert A. Sadler - Roanoke VA
Andrew H. Peake - Roanoke VA

Assignee:

ITT Corporation - New York NY

International Classification:

H01L 2976
H01L 2994
H01L 31062
H01L 31113

US Classification:

257336

Abstract:

An improved substantially planar and easy to manufacture field-effect-transistor (FET) includes a guard region between an n. sup. + drain region and the remainder of the device, which enables the breakdown voltage of the FET to be substantially increased under open-channel conditions without adversely impacting other important device characteristics.

US Patent:

55366660, Jul 16, 1996

Filed:

Mar 16, 1995

Appl. No.:

8/405174

Inventors:

Dain C. Miller - Roanoke VA
Robert A. Sadler - Roanoke VA
Andrew H. Peake - Roanoke VA

Assignee:

ITT Corporation - New York NY

International Classification:

H01L 21265

US Classification:

437 41

Abstract:

An improved substantially planar and easy to manufacture field-effect-transistor (FET) includes a guard region between an n+ drain region and the remainder of the device, which enables the breakdown voltage of the FET to be substantially increased under open-channel conditions without adversely impacting other important device characteristics.

US Patent:

48493767, Jul 18, 1989

Filed:

Dec 23, 1987

Appl. No.:

7/137482

Inventors:

Matthew L. Balzan - Roanoke VA
Arthur E. Geissberger - Roanoke VA
Robert A. Sadler - Roanoke VA

Assignee:

ITT A Division of ITT Corporation Gallium Arsenide Technology Center - Roanoke VA

International Classification:

H01L 21283

US Classification:

437228

Abstract:

A process for manufacturing GaAs FET's having refractory metal gates provides for reducing the size of the gate relative to a mask by an etch sequence which results in precisely controlled and repeatable self-limited undercutting of the mask. A reactive ion etch of the refractory metal in a CF. sub. 4 O. sub. 2 plasma containing an inert gas provides the self-limiting undercut at a pressure in the range of 175-250 mTorr when the power is less than 0. 15 W/cm. sup. 2. Preceeding the undercut, an anisotropic RIE in a CF. sub. 4 plasma can be employed to clear unmasked areas of the refractory metal and an initial sputter cleaning in argon improves the quality of the initial etch.

US Patent:

49652184, Oct 23, 1990

Filed:

Aug 23, 1988

Appl. No.:

7/235393

Inventors:

Arthur E. Geissberger - Roanoke VA
Robert A. Sadler - Roanoke VA
Paulette Luper - Salem VA
Matthew L. Balzan - Roanoke VA

Assignee:

ITT Corporation - New York NY

International Classification:

H01L 21338

US Classification:

437 41

Abstract:

A method of providing a self-aligned gate (SAG) transistor or FET is disclosed. The method permits large aligment tolerances during manufacture of the SAG FET. A reduction in gate resistance is accomplished by including a second layer of gate metallization, which is highly conductive, after the n+ implant and activation anneal without any critical realignment to the first layer of gate metal. The provision of the second layer after the anneal precludes degradation of the conductivity of the second gate metal by interdiffusion with the first (refractory) gate metal during the anneal. The large tolerance for misalignment of the gate mask level is obtained by a planarization of the anneal cap until the top surface of the first layer of gate metal is exposed, all without the need for a separate mask and etch step to open contact "windows" through the planarization anneal cap layers. The remaining adjacent encapsulant then acts as an insulator over the FET channel region and allows for gross misalignment of the second gate metallization without FET performance degradation. Using this technique, substantially increased performance can be obtained from a self-aligned FET while maintaining the basic simplicity of the RG process.

US Patent:

48472123, Jul 11, 1989

Filed:

Dec 23, 1987

Appl. No.:

7/137309

Inventors:

Matthew L. Balzan - Roanoke VA
Arthur E. Geissberger - Roanoke VA
Robert A. Sadler - Roanoke VA

Assignee:

ITT Gallium Arsenide Technology Center - Roanoke VA

International Classification:

H01L 21265
H01L 21283

US Classification:

437 41

Abstract:

The provision of an intermediately doped transition region between respective n+ implanted source and drain regions in a GaAs FET and the lightly doped channel region under the gate permits device optimizaiton for low source and drain resistance in EFET's while employing the same n+ implant for source and drain optimization in DFET's while also maintaining the same n+ to gate contact spacing in both device types. Additionally, in high frequency operation of an asymmetrically implanted FET, the tapered doping profile offered by the transition region on the drain side of the gate provides high transconductance without sacrificing high output resistance. The transition region can be provided in a self-aligned implant employing dielectric sidewall spacers and the n+ implant can be self-aligned with an etch mask employed in gate definition.

US Patent:

49563084, Sep 11, 1990

Filed:

Jan 20, 1987

Appl. No.:

7/004992

Inventors:

Edward L. Griffin - Roanoke VA
Robert A. Sadler - Roanoke VA
Arthur E. Geissberger - Roanoke VA

Assignee:

ITT Corporation - New York NY

International Classification:

H01L 21338

US Classification:

437 41

Abstract:

A self-aligned gate (SAG) transistor or FET is described which transistor overcomes several disadvantages of the prior art for making SAG field-effect transistors. The disadvantages noted above result from the fact that current SAG FET's have a symmetrical structure, with n+ regions on either side of the gate electrode. This invention provides a means of masking off a region on the drain side of the gate electrode before performing an n+ implant, so that the n+ implanted region is asymmetrical on the two sides of the gate electrode. This has the desired beneficial effect of reducing the parasitic source resistance, without the deleterious effects on gate-drain breakdown voltage, gate-drain capacitance, and output resistance that invariably accompany a high doping level on the drain side of the gate. Using this technique, substantially increased performance can be obtained from a self-aligned FET.

US Patent:

49184938, Apr 17, 1990

Filed:

Aug 10, 1988

Appl. No.:

7/230625

Inventors:

Arthur E. Geissberger - Roanoke VA
Robert A. Sadler - Roanoke VA
Gregory E. Menk - Roanoke VA
Matthew L. Balzan - Roanoke VA

Assignee:

ITT Corporation - New York NY

International Classification:

H01L 2712

US Classification:

357 4

Abstract:

A composite buffer layer is formed with a layer of GaAs on a semi-insulating GaAs substrate. Next a short period superlattice is formed followed by another GaAs layer. A layer of GaAlAs is then provided such that the Ai content and no doping followed by an intrinsic GaAs layer. The intrinsic GaAs layer is the active layer which serves as a channel.

US Patent:

49620509, Oct 9, 1990

Filed:

Dec 6, 1988

Appl. No.:

7/280780

Inventors:

Arthur E. Geissberger - Roanoke VA
Robert A. Sadler - Roanoke VA
Gregory E. Menk - Roanoke VA
Matthew L. Balzan - Roanoke VA

Assignee:

ITT Corporation - New York NY

International Classification:

H01L 21265
H01L 2144

US Classification:

437 22

Abstract:

A high speed GaAs FET is provided by forming a sandwiched GaAs channel between AlGaAs layers and employing an Si implant to provide channel doping for the GaAs channel. The poor activation efficiency of Si in AlGaAs relative to its activation efficiency in GaAs provides a channel having a higher active dopant concentration than exists in the adjacent sandwiching layers. This tends to enhance conductivity in the channel relative to the sandwiching layers.