Robert Sharp

US Patent:

6516352, Feb 4, 2003

Filed:

Aug 17, 1998

Appl. No.:

09/135074

Inventors:

Bradley J. Booth - Austin TX
Robert O. Sharp - Round Rock TX
William Kass - Austin TX

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1516

US Classification:

709250, 370463

Abstract:

A system and method for dynamically switching between different physical layer devices (PHYs) in a network interface. The system comprises a network interface in a network device, e. g. , a network card in a computer system which includes a first PHY device and a second PHY device. The first PHY device is coupled to a first transmission medium (such as fiber-optic cable) which requires a continuous connection to the computer system when active. For a SERDES device, this continuous connection is required because the PHY needs constant access to its physical coding sublayer (PCS), which is located external to the PHY. The second PHY device is coupled to a second transmission medium (such as copper cable) which does not require this continuous connection. This second PHY may be, for example, a G/MII device, which includes the PCS internally. The network interface card further includes a link switching unit, a physical layer interface unit, and a control unit.

US Patent:

7849232, Dec 7, 2010

Filed:

Feb 17, 2006

Appl. No.:

11/356501

Inventors:

Robert O. Sharp - Round Rock TX, US
Kenneth G. Keels - Georgetown TX, US
Brian S. Hausauer - Austin TX, US
John S. Lacombe - Austin TX, US

Assignee:

Intel-NE, Inc. - Wilmington DE

International Classification:

G06F 3/00
G06F 15/167
G06F 15/173
G06F 9/455

US Classification:

710 8, 709212, 709223, 709226, 718 1, 718100

Abstract:

A flexible arrangement allows a single arrangement of Ethernet channel adapter (ECA) hardware functions to appear as needed to conform to various operating system deployment models. A PCI interface presents a logical model of virtual devices appropriate to the relevant operating system. Mapping parameters and values are associated with the packet streams to allow the packet streams to be properly processed according to the presented logical model and needed operations. Mapping occurs at both the host side and at the network side to allow the multiple operations of the ECA to be performed while still allowing proper delivery at each interface.

US Patent:

8032664, Oct 4, 2011

Filed:

Sep 2, 2010

Appl. No.:

12/874739

Inventors:

Robert O. Sharp - Round Rock TX, US
Kenneth G. Keels - Georgetown TX, US
Brian S. Hausauer - Austin TX, US
John S. Lacombe - Austin TX, US

Assignee:

Intel-Ne, Inc. - Wilmington DE

International Classification:

G06F 3/00
G06F 15/167
G06F 15/173
G06F 9/455

US Classification:

710 8, 709212, 709223, 709226, 718 1, 718100

Abstract:

A flexible arrangement allows a single arrangement of Ethernet channel adapter (ECA) hardware functions to appear as needed to conform to various operating system deployment models. A PCI interface presents a logical model of virtual devices appropriate to the relevant operating system. Mapping parameters and values are associated with the packet streams to allow the packet streams to be properly processed according to the presented logical model and needed operations. Mapping occurs at both the host side and at the network side to allow the multiple operations of the ECA to be performed while still allowing proper delivery at each interface.

US Patent:

8078743, Dec 13, 2011

Filed:

Feb 17, 2006

Appl. No.:

11/356493

Inventors:

Robert O. Sharp - Round Rock TX, US
Kenneth G. Keels - Georgetown TX, US
Brian S. Hausauer - Austin TX, US
Eric Rose - Cedar Park TX, US

Assignee:

Intel-NE, Inc. - Wilmington DE

International Classification:

G06F 15/16

US Classification:

709230, 709223, 709250, 709233, 370412, 370419

Abstract:

A computer system such as a server pipelines RNIC interface (RI) management/control operations such as memory registration operations to hide from network applications the latency in performing RDMA work requests caused in part by delays in processing the memory registration operations and the time required to execute the registration operations themselves. A separate QP-like structure, called a control QP (CQP), interfaces with a control processor (CP) to form a control path pipeline, separate from the transaction pipeline, which is designated to handle all control path traffic associated with the processing of RI control operations. This includes memory registration operations (MR OPs), as well as the creation and destruction of traditional QPs for processing RDMA transactions. Once the MR OP has been queued in the control path pipeline of the adapter, a pending bit is set which is associated with the MR OP. Processing of an RDMA work request in the transaction pipeline that has engendered the enqueued MR OP is permitted to proceed as if the processing of the MR OP has already been completed.

US Patent:

8271694, Sep 18, 2012

Filed:

Aug 26, 2011

Appl. No.:

13/219145

Inventors:

Robert O. Sharp - Round Rock TX, US
Kenneth G. Keels - Georgetown TX, US
Brian S. Hausauer - Austin TX, US
John S. Lacombe - Austin TX, US

Assignee:

Intel-Ne, Inc. - Wilmington DE

International Classification:

G06F 3/00
G06F 15/167
G06F 15/173
G06F 9/455

US Classification:

710 8, 709212, 709223, 709226, 718 1, 718100

Abstract:

A flexible arrangement allows a single arrangement of Ethernet channel adapter (ECA) hardware functions to appear as needed to conform to various operating system deployment models. A PCI interface presents a logical model of virtual devices appropriate to the relevant operating system. Mapping parameters and values are associated with the packet streams to allow the packet streams to be properly processed according to the presented logical model and needed operations. Mapping occurs at both the host side and at the network side to allow the multiple operations of the ECA to be performed while still allowing proper delivery at each interface.

US Patent:

8489778, Jul 16, 2013

Filed:

Aug 17, 2012

Appl. No.:

13/588733

Inventors:

Robert O. Sharp - Round Rock TX, US
Kenneth G. Keels - Georgetown TX, US
Brian S. Hausauer - Austin TX, US
John S. Lacombe - Austin TX, US

Assignee:

Intel-NE, Inc. - Wilmington DE

International Classification:

G06F 3/00
G06F 13/12
G06F 15/173

US Classification:

710 8, 710 11, 710 62, 710 64, 709220, 709227, 709229

Abstract:

A flexible arrangement allows a single arrangement of Ethernet channel adapter (ECA) hardware functions to appear as needed to conform to various operating system deployment models. A PCI interface presents a logical model of virtual devices appropriate to the relevant operating system. Mapping parameters and values are associated with the packet streams to allow the packet streams to be properly processed according to the presented logical model and needed operations. Mapping occurs at both the host side and at the network side to allow the multiple operations of the ECA to be performed while still allowing proper delivery at each interface.

US Patent:

20060236063, Oct 19, 2006

Filed:

Feb 17, 2006

Appl. No.:

11/357446

Inventors:

Brian Hausauer - Austin TX, US
Robert Sharp - Round Rock TX, US

Assignee:

NetEffect, Inc. - Austin TX

International Classification:

G06F 12/00

US Classification:

711170000

Abstract:

An RDMA enabled I/O adapter and device driver is disclosed. In response to a memory registration that includes a list of physical memory pages backing a virtually contiguous memory region, an entry in a table in the adapter memory is allocated. A variable size data structure to store the physical addresses of the pages is also allocated as follows: if the pages are physically contiguous, the physical page address of the beginning page is stored directly in the table entry and no other allocations are made; otherwise, one small page table is allocated if the addresses will fit in a small page table; otherwise, one large page table is allocated if the addresses will fit in a large page table; otherwise, a page directory is allocated and enough page tables to store the addresses are allocated. The size and number of the small and large page tables is programmable.

US Patent:

20130110959, May 2, 2013

Filed:

Oct 31, 2011

Appl. No.:

13/285299

Inventors:

ROBERT O. SHARP - Round Rock TX, US
Kenneth G. Keels - Austin TX, US

International Classification:

G06F 15/167

US Classification:

709212

Abstract:

In an embodiment of the present invention, a method includes partitioning a plurality of remote direct memory access context objects among a plurality of virtual functions, establishing a remote direct memory access connection between a first of the plurality of virtual functions, and migrating the remote direct memory access connection from the first of the plurality of virtual functions to a second of the plurality of virtual functions without disconnecting from the remote peer.