Robert L Swanson

US Patent:

8578138, Nov 5, 2013

Filed:

Aug 31, 2009

Appl. No.:

12/550737

Inventors:

Mahesh S. Natu - Portland OR, US
Thanunathan Rangarajan - Bangalore, IN
Gautam B. Doshi - Bangalore, IN
Baskaran Ganesan - Bangalore, IN
Mohan J. Kumar - Aloha OR, US
Rajesh S. Parthasarathy - Hillsboro OR, US
Frank Binns - Portland OR, US
Rajesh Nagaraja Murthy - Bangalore, IN
Robert C. Swanson - Olympia WA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/48

US Classification:

712228, 712229

Abstract:

In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

US Patent:

20190057000, Feb 21, 2019

Filed:

Aug 15, 2017

Appl. No.:

15/677325

Inventors:

- Santa Clara CA, US
Janusz P. Jurski - Hillsboro OR, US
Piotr Kwidzinski - Folsom CA, US
Robert C. Swanson - Olympia WA, US
Madhusudhan Rangarajan - Round Rock TX, US

International Classification:

G06F 11/14

Abstract:

Embodiments of the claimed invention include a computing device having a host processor for executing a firmware environment and a manageability controller. The firmware environment reserves a frame buffer in main memory and loads a graphics protocol driver to provide the frame buffer to an operating system of the computing device. The operating system renders graphical images to the frame buffer using a graphics driver. The manageability controller reads the graphical image from the frame buffer and may transmit the graphical image to a remote computing device. In response to a fatal error of the computing device, the manageability controller may store the graphical image to a non-volatile storage device. The host processor may assert a host reset signal in response to the fatal error, and the manageability controller may send an acknowledgment to the host processor after storing the graphical image. Other embodiments are described and claimed.

US Patent:

20180165207, Jun 14, 2018

Filed:

Dec 9, 2016

Appl. No.:

15/374796

Inventors:

- Santa Clara CA, US
Ashok Raj - Portland OR, US
Robert C. Swanson - Olympia WA, US
Mohan J. Kumar - Aloha OR, US

International Classification:

G06F 12/0868
G06F 11/20
G06F 12/109

Abstract:

One embodiment provides for a data processing system comprising a multi-level system memory including a first memory level of volatile memory and a second memory level that is larger and slower in comparison with the first memory level. The second memory level includes non-volatile memory and can additionally include volatile memory. The multi-level system memory includes a multi-level memory controller including logic to manage a list of faulty addresses within the multi-level system memory. The multi-level memory controller can manage a list of faulty addresses. The multi-level memory controller is configured to satisfy a request for data stored in the first memory level from the second memory level when the data is stored in an address on the list of faulty addresses.

US Patent:

20180143923, May 24, 2018

Filed:

Jan 17, 2018

Appl. No.:

15/873089

Inventors:

- Santa Clara CA, US
Thanunathan Rangarajan - Bangalore, IN
Gautam Doshi - Bangalore, IN
Shamanna M. Datta - Hillsboro OR, US
Baskaran Ganesan - Bangalore, IN
Mohan J. Kumar - Aloha OR, US
Rajesh S. Parthasarathy - Hillsboro OR, US
Frank Binns - Portland OR, US
Rajesh Nagaraja Murthy - Bangalore, IN
Robert C. Swanson - Olympia WA, US

International Classification:

G06F 13/24
G11C 11/406
G11C 7/10
G06F 9/46
G06F 9/30
G06F 9/38

Abstract:

In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

US Patent:

20180046502, Feb 15, 2018

Filed:

Mar 23, 2015

Appl. No.:

15/553481

Inventors:

- Santa Clara CA, US
Jiewen YAO - Shanghai, CN
Sarathy JAYAKUMAR - Portland OR, US
Robert C. SWANSON - Olympia WA, US
Rajesh POORNACHANDRAN - Portland OR, US
Gopinatth SELVARAJE - Portland OR, US
Mingqiu SUN - Beaverton OR, US
John S. HOWARD - Portland OR, US
Eugene GORBATOV - Hillsboro OR, US

International Classification:

G06F 9/48
G06F 9/50
G06F 1/32

Abstract:

Methods, apparatuses and storage medium associated with migration between processors by a computing device are disclosed. In various embodiments, a portable electronic device having an internal processor and internal memory may be attached to a dock. The dock may include another processor as well other memory. The attachment of the dock to the portable electronic device may cause an interrupt. In response to this interrupt, a state associated with the internal processor may be copied to the other memory of the dock. Instructions for the computing device may then be executed using the other processor of the dock. Other embodiments may be disclosed or claimed.

US Patent:

20170286210, Oct 5, 2017

Filed:

Mar 31, 2016

Appl. No.:

15/087797

Inventors:

- SANTA CLARA CA, US
Ashok RAJ - Portland OR, US
Robert SWANSON - Olympia WA, US
Mohan J. KUMAR - Aloha OR, US

International Classification:

G06F 11/07
G06F 12/08

Abstract:

An apparatus is described that includes memory controller logic circuitry to interface with a memory side cache of a multi-level system memory. The memory controller logic circuitry includes error tracking circuitry to track errors of cache line slots in the memory side cache. The memory controller logic circuitry also comprises faulty list circuitry to store identifiers of faulty cache line slots that are deemed to be excessively error prone. The memory controller logic circuitry is to declare a miss in the memory side cache for requests that map to cache line slots identified in the faulty list.

US Patent:

20170010991, Jan 12, 2017

Filed:

Sep 20, 2016

Appl. No.:

15/270151

Inventors:

- Santa Clara CA, US
Thanunathan Rangarajan - Bangalore, IN
Gautam Doshi - Bangalore, IN
Shamanna M. Datta - Hillsboro OR, US
Baskaran Ganesan - Bangalore, IN
Mohan J. Kumar - Aloha OR, US
Rajesh S. Parthasarathy - Hillsboro OR, US
Frank Binns - Portland OR, US
Rajesh Nagaraja Murthy - Bangalore, IN
Robert C. Swanson - Olympia WA, US

International Classification:

G06F 13/24
G11C 7/10
G11C 11/406

Abstract:

In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

US Patent:

20150089249, Mar 26, 2015

Filed:

Sep 24, 2013

Appl. No.:

14/035534

Inventors:

William R. Hannon - Hillsboro OR, US
David P. Larsen - Hillsboro OR, US
Robert C. Swanson - Olympia WA, US

International Classification:

G06F 1/26

US Classification:

713300

Abstract:

In an embodiment, a power management controller is to receive thread information from a scheduler, where the thread information includes thread priority information for a thread scheduled to a core of a multicore processor. The power management controller is further to receive power consumption information from a power controller and to determine a power management action to be taken by the power controller on at least one core based at least in part on the thread priority information. Other embodiments are described and claimed.