Robert N Thibault

US Patent:

60612746, May 9, 2000

Filed:

Jan 4, 1999

Appl. No.:

9/224701

Inventors:

Robert A. Thibault - Raynham MA
Michael Shulman - Groton MA

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G11C 700

US Classification:

36518905

Abstract:

A computer storage system includes an array of storage devices, a system cache memory, one or more back end directors for controlling data transfer between the storage devices and the system cache memory, and one or more front end directors for controlling data transfer between the system cache memory and a host computer. Each director includes a processor and a message interface for controlling high speed message transfer between the processors in the directors. The message interfaces in the directors may be interconnected in a closed-loop configuration. Each message interface may include a transmit/receive circuit for transferring messages to and from other directors, a message memory for storing outgoing messages and incoming messages, and a message controller for controlling transfer of messages between the processor and the message memory and between the message memory and the transmit/receive circuit.