Robert E Thibault

US Patent:

6581112, Jun 17, 2003

Filed:

Mar 31, 2000

Appl. No.:

09/540675

Inventors:

Avinash Kallat - Marlborough MA
Robert Thibault - Westboro MA

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 1328

US Classification:

710 22, 711141, 711142, 711143, 711146

Abstract:

A direct memory access (DMA) receiver adapted to receive data from a source, such data to be written into a random access memory is provided. The random access memory and DMA receiver being coupled are to a central processing unit by a bus. The central processing unit is coupled to a local cache memory. The source of such data provides an address for the data, such address being the location the random access memory where the data is to be stored. The DMA receiver includes an address register, a first data register and a duplicate data register. The duplicate register has an input coupled to an output of the first data register. A selector is provided having a pair of inputs, one being coupled to the output of the first data register and another one of the pair of inputs being coupled to an output of the duplicate data register. The selector couples one of the pair of inputs to an output thereof selectively in accordance with a select signal. A state machine is included in the DMA receiver.

US Patent:

6584513, Jun 24, 2003

Filed:

Mar 31, 2000

Appl. No.:

09/540827

Inventors:

Avinash Kallat - Marlborough MA
Robert Thibault - Westboro MA

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 1300

US Classification:

710 22, 711135, 711143, 711146

Abstract:

A direct memory access (DMA) transmitter includes: (a) a data register; and (b) a transmitter state machine. Requested data at an address provided by a source is read from the random access memory then transferred for storage in the data register. The central processing unit also sends a control signal to the transmit state machine. The control signal indicates to the transmit state machine whether the read data is a most recent copy of the requested data in random access memory or whether the most recent copy of the requested data is still resident in the local cache memory. In response to the control signal, if the most recent data is in the local cache memory, the transmit state machine inhibits the data that was read from random access memory and now stored in data register from passing to the transmitter output. Transmit state machine then performs a second data transfer request at the same address, the second requested data being transferred from the local cache memory to the random access memory. The transmit state machine reads the second requested data from the random access memory.

US Patent:

6651130, Nov 18, 2003

Filed:

Apr 28, 2000

Appl. No.:

09/561532

Inventors:

Robert Thibault - Westboro MA

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 100

US Classification:

710317, 710316, 710309, 710 29, 710 31, 711112, 711114

Abstract:

A system interface includes a plurality of first directors, a plurality of second directors, a data transfer section and a message network. The data transfer section includes a cache memory. The cache memory is coupled to the plurality of first and second directors. The messaging network operates independently of the data transfer section and such network is coupled to the plurality of first directors and the plurality of second directors. The first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the messaging network to facilitate data transfer between first directors and the second directors. The data passes through the cache memory in the data transfer section. A method for operating a data storage system adapted to transfer data between a host computer/server and a bank of disk drives.

US Patent:

6779071, Aug 17, 2004

Filed:

Apr 28, 2000

Appl. No.:

09/561531

Inventors:

Avinash Kallat - Marlborough MA
Robert Thibault - Westboro MA
Stephen D. MacArthur - Northborough MA

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 1300

US Classification:

710317

Abstract:

A system interface includes a plurality of first directors, a plurality of second directors, a data transfer section and a message network. The data transfer section includes a cache memory. The cache memory is coupled to the plurality of first and second directors. The messaging network operates independently of the data transfer section and such network is coupled to the plurality of first directors and the plurality of second directors. The first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the messaging network to facilitate data transfer between first directors and the second directors. The data passes through the cache memory in the data transfer section. A method for operating a data storage system adapted to transfer data between a host computer/server and a bank of disk drives.

US Patent:

6868479, Mar 15, 2005

Filed:

Mar 28, 2002

Appl. No.:

10/109603

Inventors:

Robert A. Thibault - Westboro MA, US
Stephen D. MacArthur - Northboro MA, US
Brian Gallagher - Southboro MA, US
Brian Marchionni - Milford MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F012/00

US Classification:

711114, 710305

Abstract:

A data storage system for transferring data between a host computer/server and a bank of disk drives through a system interface. The system interface includes: a plurality of first directors coupled to the host computer/server; a plurality of second directors coupled to the bank of disk drives; a cache memory; and a data transfer section coupled to the plurality of first directors, the second directors, and the cache memory. A messaging network is coupled to the plurality of first directors and the plurality of second directors. The first and second directors control data transfer between the host computer and the bank of disk drives in response to messages passing between the directors through the messaging network as such data passes through the memory via the data transfer section. A service processing network is provided for interfacing a plurality of service processing units to the plurality of first and second directors through a plurality of redundant communication channels. With such arrangement, because the service processor is being more involved in the functionality operation of the system, a pair of redundant service processors is provided.

US Patent:

6877061, Apr 5, 2005

Filed:

Mar 28, 2002

Appl. No.:

10/112598

Inventors:

Robert A. Thibault - Westboro MA, US
Daniel Castel - Boston MA, US
Brian Gallagher - Southboro MA, US
Paul C. Wilson - Mendon MA, US
John K. Walton - Mendon MA, US
Christopher S. MacLellan - Walpole MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F013/00
G06F013/14
H05K007/10

US Classification:

710312, 710305, 710313, 710316, 710104, 710300

Abstract:

A method and system for producing a data storage system for transferring data between a host computer/server and a bank of disk drives through a system interface. The system interface has a plurality of first directors, a plurality of second directors, and a global memory. The method includes: providing a backplane having slots adapted to have plugged therein a plurality of printed circuit board. The printed circuit boards include: a plurality of first director boards having the first directors; a plurality of second printed circuit boards having the second directors; a plurality of memory printed circuit boards providing the global memory; a plurality of dummy first director boards having first jumpers; a plurality of dummy second director boards having second jumpers; a plurality of dummy memory boards having third jumpers. The method includes wiring the backplane to effect a connection among the first, second and third jumpers to interconnect the first plurality of director to the host computer/server, the plurality of second plurality of directors to the bank of disk drives and the global memory to the first plurality of directors and to the second plurality of director. The method and system allows the same wired backplane to be used with systems having a different number of memory and director boards and still enable dual-write and redundancy to the global memory.

US Patent:

6907483, Jun 14, 2005

Filed:

Mar 28, 2002

Appl. No.:

10/109583

Inventors:

Daniel Castel - Boston MA, US
Robert A. Thibault - Westboro MA, US
Brian Gallagher - Southboro MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F013/12

US Classification:

710 74, 710 2, 710 62, 710301, 709203, 709213, 711147

Abstract:

A method and system for producing a data storage system for transferring data between a host computer/server and a bank of disk drives through a system interface. The system interface has a plurality of first directors, a plurality of second directors, and a global memory. The method includes: providing a backplane having slots adapted to have plugged therein a plurality of printed circuit board. The printed circuit boards include: a plurality of first director boards having the first directors; a plurality of second printed circuit boards having the second directors; a plurality of memory printed circuit boards providing the global memory; a plurality of dummy first director boards having first jumpers; a plurality of dummy second director boards having second jumpers; a plurality of dummy memory boards having third jumpers. The method includes wiring the backplane to effect a connection among the first, second and third jumpers to interconnect the first plurality of director to the host computer/server, the plurality of second plurality of directors to the bank of disk drives and the global memory to the first plurality of directors and to the second plurality of director. The method and system allows the same wired backplane to be used with systems having a different number of memory and director boards and still enable dual-write and redundancy to the global memory.

US Patent:

7007194, Feb 28, 2006

Filed:

Jun 29, 2000

Appl. No.:

09/606730

Inventors:

Paul C. Wilson - Mendon MA, US
Mark Zani - Salem MA, US
Farouk Khan - Wilmington MA, US
Christopher S. MacLellan - Norwood MA, US
John K. Walton - Mendon MA, US
Steven MacArthur - Northboro MA, US
Kendall A. Chilton - Southboro MA, US
William Tuccio - Sutton MA, US
Robert A. Thibault - Westboro MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 11/00

US Classification:

714 6, 714 4, 714 42, 711112, 711113

Abstract:

A system interface includes a plurality of first directors, a plurality of second directors, a data transfer section and a message network. The data transfer section includes a cache memory. The cache memory is coupled to the plurality of first and second directors. The messaging network operates independently of the data transfer section and such network is coupled to the plurality of first directors and the plurality of second directors. The first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the messaging network to facilitate data transfer between first directors and the second directors. The data passes through the cache memory in the data transfer section. A method for operating a data storage system adapted to transfer data between a host computer/server and a bank of disk drives.