Robert C Todd

US Patent:

6973633, Dec 6, 2005

Filed:

Jul 24, 2002

Appl. No.:

10/206691

Inventors:

George Lippincott - Lake Oswego OR, US
Nick Cobb - San Jose CA, US
Robert Todd - Tualatin OR, US

International Classification:

G06F017/50

US Classification:

716 11, 716 2, 716 19

Abstract:

One or more control points are identified within a reticle layout that is used in a simulation of a manufacturing process for an integrated device layer. Further, a current geometrical layout pattern is determined in the vicinity of the control points, and a cache is searched for a matching geometrical layout pattern. If the search is successful, a simulation result associated with the matching geometrical layout pattern is retrieved from the cache and reused for the current geometrical layout pattern. Alternatively, if the search is unsuccessful, a simulation result associated with the current geometrical design pattern is computed and stored in the cache for future reuse.

US Patent:

20040083475, Apr 29, 2004

Filed:

Oct 25, 2002

Appl. No.:

10/280710

Inventors:

Robert Todd - Tualatin OR, US
Laurence Grodd - Portland OR, US
Nicolas Cobb - San Jose CA, US

Assignee:

Mentor Graphics Corp. - Wilsonville OR

International Classification:

G06F009/00

US Classification:

718/102000

Abstract:

A method and tool are disclosed for distributing operations in a software application from a master computer to one or more slave computers for execution. Operations within the software application are identified that employ input data independent of other input data. The identified operations, which can be organized into groups of one or more operations, may then be distributed to a slave computer for execution. A group of operations may also include one or more heuristics, for determining when the group of operations should be executed on a slave computer. If a group of operations is distributed to a slave computer for execution, the master computer subsequently determines if the slave computer successfully executed those operations. If the slave computer successfully executed the group of operations, it returns the results to the master computer, which then employs the returned results to continue running the software application. If, however, the slave computer was unable to successfully execute the group of operations, then the master computer may execute the group of operations itself or provide the group of operations to another slave computer, allowing the master computer to continue running the software application without interruption.

US Patent:

20070233805, Oct 4, 2007

Filed:

Apr 2, 2006

Appl. No.:

11/396929

Inventors:

Laurence Grodd - Portland OR, US
Robert Todd - Sherwood OR, US
Jimmy Tomblin - Portland OR, US

Assignee:

Mentor Graphics Corp. - Wilsonville OR

International Classification:

G06F 15/16

US Classification:

709208000

Abstract:

Parallel operation sets for use by a software application are identified. Each parallel operation set is then provided to a master computing thread for processing, together with its associated process data. Each master computing thread will then provide its operation set to one or more slave computers based upon parallelism in the process data associated with its operation set. In this manner, the execution of operations by a software application is widely distributed among multiple networked computers based upon parallelism in both the process data used by the software and the operations executed by the software application.

US Patent:

20080235497, Sep 25, 2008

Filed:

Nov 26, 2007

Appl. No.:

11/945263

Inventors:

Jimmy J. Tomblin - Portland OR, US
Laurence W. Grodd - Portland OR, US
Robert A. Todd - Sherwood OR, US

International Classification:

G06F 9/315

US Classification:

712225, 712E09034

Abstract:

Multiple processing threads operate in parallel to convert data, produced by one or more electronic design automation processes in an initial format, into another data format for output. A processing thread accesses a portion of the initial results data produced by one or more electronic design automation processes in an initial format and in an initial organizational arrangement. The processing thread will then store data within this portion of the initial results data belonging to a target category of the desired output organizational arrangement, such as a cell, at a memory location corresponding to that target category. It will also convert the stored data from a first data format to another data format for output. The first data format may use a relatively low amount of compression, with the second data format may use a relatively high level of compression. Each of a plurality of processing threads may operate in this manner in parallel upon portions of the initial results data, until all of the initial results data has been converted to the desired data format for output. A processing thread can then collect the converted data from the various memory locations, and provide it as output data for the electronic design automation process or processes.

US Patent:

6230299, May 8, 2001

Filed:

Mar 31, 1998

Appl. No.:

9/052895

Inventors:

Michael C. McSherry - Portland OR
Richard E. Strobel - Vancouver WA
Robert A. Todd - Tigard OR
Paul M. Nguyen - Beaverton OR

Assignee:

Mentor Graphics Corporation - Wilsonville OR

International Classification:

G06S 1750

US Classification:

716 1

Abstract:

A data extraction tool is provided to extract filtered connectivity and geometrical data for specified layout cell hierarchies of an integrated circuit (IC) design, e. g. a deep sub-micron IC design. The connectivity and geometrical data for each layout cell hierarchy are extracted at least in part in accordance with specified parasitic effect windows. In one embodiment, the data extraction tool includes a filtered extraction function that operates to extract connectivity and geometrical data for layout nets of each layout cell hierarchy of the IC design, one or more layout nets at a time. Additionally, one or more filtered databases are provided to store the filtered connectivity and geometrical data of the layout cell hierarchies.

US Patent:

56163002, Apr 1, 1997

Filed:

May 24, 1995

Appl. No.:

8/448669

Inventors:

Douglas W. Ford - West Linn OR
Robert W. Todd - Gresham OR
Quinn E. Trammell - Gresham OR
Dennis A. Higley - Oregon City OR

Assignee:

Optimize Technologies, Inc. - Portland OR

International Classification:

G01N 3510

US Classification:

422103

Abstract:

A valve (10) is used to introduce fluid from a syringe (22) into the inlet (88) of the pump of an HPLC instrument (12). The valve includes a valve body (14) that is connected to the HPLC instrument for fluid flow communication with the instrument inlet. A valve rotor (16) is rotatably engaged with the valve body. A collar fitting (18) included on the valve rotor is connectable to the syringe. The syringe acts as a valve lever, and is displaceable to rotate the valve rotor about an axis of rotation (32) between an "off" position, in which fluid flow between the syringe and the HPLC instrument inlet is prevented, and an "on" position, in which fluid flow between the syringe and the HPLC instrument inlet is permitted. The valve enables one-handed priming operation.

US Patent:

45454175, Oct 8, 1985

Filed:

Jun 20, 1983

Appl. No.:

6/506023

Inventors:

Robert W. Todd - Wilsonville OR

International Classification:

E05D 1526

US Classification:

160207

Abstract:

An overhead door, particularly intended for use in a structure having a wide opening, includes an upper section pivotally mounted by hinges to the header beam of the structure, and a taller lower section pivotally mounted to the bottom of the upper section by hinges. Guide tracks are mounted on the side door jambs of the building, and guide rollers are mounted adjacent each lateral side edge of the lower section arranged to be movably captured by the guide tracks during folding and unfolding of the door in opening and closing. A plurality of lift cables are connected at one of their ends to laterally spaced positions along the width of the lower door section and at the same height preferably above its vertical midpoint but below the point where the upper and lower sections are hinged together by a distance equal to or greater than the height of the upper section. The opposite ends of the lift cables are connected to a counterbalance.

US Patent:

62499033, Jun 19, 2001

Filed:

Mar 31, 1998

Appl. No.:

9/052915

Inventors:

Michael C. McSherry - Portland OR
Richard E. Strobel - Vancouver WA
Robert A. Todd - Tigard OR
Paul M. Nugyen - Beaverton OR

International Classification:

G06F 1750

US Classification:

716 11

Abstract:

A parasitic extraction tool (PEX) is provided to generate electrical modeling data for an integrated circuit (IC) design, e. g. a deep sub-micron IC design. The PEX includes a read function for reading extracted connectivity and geometrical data of various layout cell hierarchies of the IC design, that are organized and indexed by layout nets. The PEX also includes a write function for writing generated electrical modeling data into a parasitic database (PDB), which is physically organized to accommodate physical storage of the electrical modeling data in multiple physical media, and concurrent usage of the electrical data by multiple client applications, e. g. post layout analysis tool. In one embodiment, the PDB further includes an application interface that shields the physical organization of the PDB, and a logical abstraction of the physical organization to facilitate implementation of the application interface.