Robert D Waldron

US Patent:

6476497, Nov 5, 2002

Filed:

Mar 26, 2001

Appl. No.:

09/817642

Inventors:

Robert D. Waldron - Fort Collins CO
Rich Schultz - Fort Collins CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2182

US Classification:

257775, 438129, 438597, 438598, 438637, 257691, 257692, 257773

Abstract:

A method for concentric metal density power distribution is disclosed that reduces metal density and increases available area for routing clock and signal traces. A method of concentric metal density power distribution includes the steps of partitioning an area of standard cells in an integrated circuit chip into a plurality of power regions, forming a power boundary around each of the plurality of power regions, and forming a plurality of concentric straps in a metal layer of the integrated circuit chip wherein each of the plurality of concentric straps has a strap width that varies from a maximum strap width at a periphery of each of the plurality of power regions to a minimum strap width toward a center of each of the plurality of power regions.

US Patent:

7292063, Nov 6, 2007

Filed:

May 2, 2005

Appl. No.:

11/120067

Inventors:

Scott C. Savage - Fort Collins CO, US
Robert D. Waldron - Fort Collins CO, US
Donald T. McGrath - Fort Collins CO, US
Kenneth G. Richardson - Erie CO, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G06F 7/38
H01L 25/00

US Classification:

326 38, 326 37, 326 41, 326 47, 326101

Abstract:

A method for interconnecting sub-functions of metal-mask programmable functions that includes the steps of (A) forming a base layer of a platform application specific integrated circuit (ASIC) comprising a plurality of pre-diffused regions disposed around a periphery of the platform ASIC, (B) forming two or more sub-functions of a function with a metal mask set placed over a number of the plurality of pre-diffused regions of the platform application specific integrated circuit and (C) configuring one or more connection points in each of the two or more sub-functions such that interconnections between the two or more sub-functions are tool routable in a single layer. Each of the pre-diffused regions is configured to be metal-programmable.

US Patent:

7305646, Dec 4, 2007

Filed:

May 9, 2005

Appl. No.:

11/125307

Inventors:

Donald T. McGrath - Fort Collins CO, US
Robert D. Waldron - Fort Collins CO, US
Scott C. Savage - Fort Collins CO, US
Kenneth G. Richardson - Erie CO, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G06F 17/50
H03K 19/173

US Classification:

716 12, 716 1, 326 38

Abstract:

An apparatus that may include a base layer of a platform application specific integrated circuit (ASIC) and a mixed-signal function. The base layer of the platform application specific integrated circuit (ASIC) generally comprises a plurality of pre-diffused regions disposed around a periphery of the platform ASIC. Each of the pre-diffused regions may be configured to be metal-programmable. The mixed-signal function may include two or more sub-functions formed with a metal mask set placed over a number of the plurality of pre-diffused regions.

US Patent:

7360178, Apr 15, 2008

Filed:

May 24, 2005

Appl. No.:

11/136180

Inventors:

Scott C. Savage - Fort Collins CO, US
Donald T. McGrath - Fort Collins CO, US
Robert D. Waldron - Fort Collins CO, US
Kenneth G. Richardson - Erie CO, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 17/50

US Classification:

716 1

Abstract:

A method for producing a chip is disclosed. A first step of the method may include fabricating the chip only up to and including a first metal layer such that a core region of the chip has an array of cells, each of the cells having a plurality of transistors. A second step generally involves designing a plurality of upper metal layers above the first metal layer in response to a custom design created after the first fabricating has started, the upper metal layers interconnecting a plurality of the cells to form (i) a mixed-signal module and (ii) a digital module, the mixed signal module generating at least one analog signal and at least one digital signal. In a third step, the method may include fabricating the chip to add the upper metal layers.

US Patent:

7373622, May 13, 2008

Filed:

May 13, 2005

Appl. No.:

11/129547

Inventors:

Scott C. Savage - Fort Collins CO, US
Donald T. McGrath - Fort Collins CO, US
Robert D. Waldron - Fort Collins CO, US
Kenneth G. Richardson - Erie CO, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 17/50

US Classification:

716 4, 716 5, 716 6

Abstract:

An apparatus including a base layer of a platform application specific integrated circuit (ASIC), a mixed-signal function and a built-in self test (BIST) function. The base layer of the platform ASIC generally includes a plurality of pre-diffused regions disposed around a periphery of the platform ASIC. Each of the pre-diffused regions is generally configured to be metal-programmable. The mixed-signal function may include two or more sub-functions formed with a metal mask set placed over a first number of the plurality of pre-diffused regions. The BIST function may be formed with a metal mask set placed over a second number of the plurality of pre-diffused regions. The BIST function may be configured to test the mixed-signal function and present a digital signal indicating an operating condition of the mixed-signal function.

US Patent:

7373629, May 13, 2008

Filed:

Apr 25, 2005

Appl. No.:

11/113615

Inventors:

Donald T. McGrath - Fort Collins CO, US
Scott C. Savage - Fort Collins CO, US
Robert D. Waldron - Fort Collins CO, US
Kenneth G. Richardson - Erie CO, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 17/50
G05F 1/40

US Classification:

716 17

Abstract:

An apparatus comprising an integrated circuit having (i) a number of regions each pre-diffused and configured to be metal-programmed and (ii) a plurality of pins configured to connect the integrated circuit to a socket. A logic portion may be implemented on the integrated circuit (i) configured to implement integrated circuit operations and (ii) having one or more I/O connections and one or more supply connections. A first group of the pre-diffused regions are metal-programmed and coupled to said I/O connections. A second group of the pre-diffused regions are metal-programmed and coupled to the supply connections.

US Patent:

7424690, Sep 9, 2008

Filed:

Dec 7, 2004

Appl. No.:

11/005690

Inventors:

Richard T Schultz - Fort Collins CO, US
Robert Waldron - Fort Collins CO, US
Norman Mause - Fort Collins CO, US
Larry Greenhouse - San Diego CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G06F 17/50

US Classification:

716 5, 716 4, 716 10, 716 11

Abstract:

A system and method for designing a complex electronic circuit by simulating blocks of the circuit using various simulators to produce a net list, designing the physical layout of the circuit using a layout tool that produces a layout verses schematic reference file, mapping the reference file to the net list to create a mapping file, and analyzing the mapping file to verify that the layout meets various criteria. Each block may be verified using simulation tools that are appropriate for that piece of the overall circuit, and using conditions that may maximize the strain on the circuit. The results from the simulations are compared to the physical layout to determine if the physical layout is able to properly conduct the electrical signals.

US Patent:

7478354, Jan 13, 2009

Filed:

May 20, 2005

Appl. No.:

11/133815

Inventors:

Donald T. McGrath - Fort Collins CO, US
Scott C. Savage - Fort Collins CO, US
Robert D. Waldron - Fort Collins CO, US
Kenneth G. Richardson - Erie CO, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G06F 17/50

US Classification:

716 12, 716 13, 716 14

Abstract:

A method for producing a chip is disclosed. A first step of the method may involve fabricating the chip only up to and including a first metal layer during a first manufacturing phase such that an input/output (I/O) region of the chip has a plurality of slots, where each of the slots has a plurality of first transistors. A second step of the method may involve designing a plurality of upper metal layers above the first metal layer in response to a custom design created after the first fabricating has started, the upper metal layers interconnecting a plurality of the first transistors to form a plurality of mixed-signal building block functions. A third step of the method may involve fabricating the chip to add the upper metal layers during a second manufacturing phase.