Robert J Walsh

US Patent:

6868434, Mar 15, 2005

Filed:

Aug 7, 2000

Appl. No.:

09/633476

Inventors:

Mark C. Terranova - Maynard MA, US
Michael P. Shea - Nashua NH, US
Robert E. Walsh - Foster City CA, US
Michael V. Iarrobino - Bedford NH, US
Michael J. Stokes - Beckenham, GB

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F015/16

US Classification:

709203, 709217

Abstract:

A system and method for testing server latencies using multiple concurrent users in a computer system is provided. A computer system may include a server and one or more clients. Multiple users may be created in the system such that each user may login to the server. The server may include a directory for each user and the directory for each user may be populated with a mix of files according to a user type for each user. An instance of a test program may be executed for each user on one or more clients concurrently. The server may authenticate each user using the same or different operating system protocols. Each instance of the test program may be configured to cause a series of accesses to one or more files in the directory of its respective user on the server and may be configured to cause a latency value to be measured and stored for each access that is performed. The latency values may be compiled by each instance of the test program and may be stored onto the server upon completion of each instance of the test program. The latency values measured by an instance of the test program may represent a first time portion that corresponds to the amount of time to perform a given access and a second time portion that corresponds to the server verifying that the user corresponding to this instance of the test program has permission to access the file.

US Patent:

6886107, Apr 26, 2005

Filed:

Nov 15, 2001

Appl. No.:

09/999156

Inventors:

Robert J. Walsh - Ashland MA, US
Steve N. Barbas - Billerica MA, US
James F. Friend - Pepperell MA, US

Assignee:

Marconi Intellectual Property (Ringfence), Inc. - Warrendale PA

International Classification:

G06F011/00

US Classification:

714 4

Abstract:

A system and method for configuring a control plane within a network device. One of a pair of control processors is selected to act as the master of the control plane and the other control processor is specified as a standby control processor in normal operation. In the case of a failover or switchover event, the standby control processor assumes the role of the master of the control plane and updates configuration information within line cards in the network device as necessary. A state machine within the control processor is employed to manage state transitions for the control processor. Each control processor generates at least one signal that indicates whether it is capable of serving as the master of the control plane. Master selection logic selects one of the control processors as the master for the control plane and in one embodiment advertises the identification of the master control processor via triply redundant signals. Voting logic within the control processors and other cards within the network device is employed to identify the selected master unit for the control plane.

US Patent:

7260648, Aug 21, 2007

Filed:

Jan 22, 2002

Appl. No.:

10/054522

Inventors:

Chase T. Tingley - Somerville MA, US
Robert J. Walsh - Ashland MA, US

Assignee:

Ericsson, Inc. - Warrendale PA

International Classification:

G06F 15/16

US Classification:

709245, 709238, 709242, 709227, 709228

Abstract:

A system for supporting translation of virtual IP addresses to Ethernet/MAC addresses in a multi-Virtual Network environment, in which address resolution tables are generated and maintained by Virtual Networking Devices. Virtual Networking Device (VND) sends and/or receives Virtual Network-specific ARP traffic. The Virtual Network-specific ARP traffic includes ARP requests or responses that map a MAC address to an IP address in the private IP address space of an associated Virtual Private Network. The disclosed Virtual Networking Devices can therefore operate in configurations in which multiple independent entities operate on separate Virtual Networks, and where servers may be accessible via virtual IP addresses within the private IP address spaces of associated Virtual Networks.

US Patent:

56131291, Mar 18, 1997

Filed:

May 2, 1994

Appl. No.:

8/236930

Inventors:

Robert J. Walsh - Ashland MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 1324

US Classification:

395740

Abstract:

Postponing the interrupt for an I/O event can increase system throughput by amortizing the cost of the interrupt service routine over multiple I/O events. In current systems that provide interrupt postponement, the time parameter is fixed. Fixed values can lead to parameter configuration errors, excessive characterization work to generate parameter values, and a failure to automatically re-configure to system changes or to external load changes. The proposed mechanism measures actual system experience and eliminates the parameter configuration effort by filtering its own experience to derive a target value for interrupt postponement. A current postponement value with the potentially greater variance than the target is used to rapidly respond to abrupt change in offered load. The invention also benefits tasks with real-time deadlines to provide correct system operation.

US Patent:

55532640, Sep 3, 1996

Filed:

Jun 24, 1994

Appl. No.:

8/265543

Inventors:

Cuneyt M. Ozveren - Somerville MA
Robert J. Walsh - Ashland MA
Greg Waters - Groton MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 1212

US Classification:

395462

Abstract:

In the present invention, one of the bits in the tag value in the cache is hard-wired, for example, to 0, at such a position in the cache that that bit is always set to 0 when a tag is stored in the cache (or forced to 0 when a tag is read from the cache). Instructions executed by the processor can specify a read outside the cache, i. e. of the most recent data written to the main memory by some DMA agent, by specifying a read address with the designated bit equal to one. In this way, a cache miss is forced, allowing the processor to read the most recent data from the main memory of the system and to cache the data. As the cache is refilled from the main memory, the hard-wired tag bit of course remains set to zero. So later processor instructions that read data within the same cache refill block would use the normal address of that data (having the designated bit set to zero). These subsequent reads will not force a cache miss.

US Patent:

57747270, Jun 30, 1998

Filed:

Dec 27, 1995

Appl. No.:

8/579457

Inventors:

Robert J. Walsh - Hopkinton MA
Bradley Miller - Westboro MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 944
G06F 945

US Classification:

395706

Abstract:

A language construct that allows a software programmer to use an intermediate or high-level language command to explicitly group operations or fuse loops in a group of statements operating on parallel arrays is disclosed. The command instructs a compiler, which would otherwise add temporary variables to avoid data dependencies or perform data dependency analysis, to translate the enclosed statements directly into machine language code without adding those temporary variables and without performing any data dependency analysis. Execution of the command results in the performance of the group of statements by all of the virtual processors.