Robert A Woods

US Patent:

6463510, Oct 8, 2002

Filed:

Dec 29, 2000

Appl. No.:

09/751505

Inventors:

Phillip M. Jones - Spring TX
Robert L. Woods - Allentown PA

Assignee:

Compaq Information Technologies Group, L.P. - Houston TX

International Classification:

G06F 1200

US Classification:

711138, 711141

Abstract:

An apparatus for identifying memory requests originating on remote I/O devices as non-cacheable in a computer system with multiple processors includes a main memory, memory cache, processor, cache coherence directory and cache coherence controller all coupled to a host bridge unit (North bridge). The I/O device transmits requests for data to an I/O bridge unit. The I/O bridge unit forwards the request for data to the host bridge unit and asserts a sideband signal to the host bridge unit if the request is for non-cacheable data. The sideband signal informs the host bridge unit that the memory request is for non-cacheable data and that the cache coherence controller does not need to perform a cache coherence directory lookup. For cacheable data, the cache coherence controller performs a cache coherence directory lookup to maintain the coherence of data stored in a plurality of processor caches in the computer system.

US Patent:

57781990, Jul 7, 1998

Filed:

Apr 26, 1996

Appl. No.:

8/638143

Inventors:

Christopher C. Wanner - Tomball TX
Robert L. Woods - Tomball TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1300

US Classification:

395287

Abstract:

A method or apparatus of blocking access to a first device via a bus carrying an address enable signal in a computer system. A second device detects appearance of predetermined bus address information, and the address enable signal is blocked from the first device if the predetermined bus address information is present. A third device connected to the bus and the first device both are responsive to the predetermined bus address information, which includes bus addresses having upper bits with a non-zero value.

US Patent:

61015660, Aug 8, 2000

Filed:

Mar 13, 1998

Appl. No.:

9/041606

Inventors:

Robert Woods - Tomball TX
Jeff W. Wolford - Spring TX
Jeffrey C. Stevens - Spring TX
Shaun Wandler - Tomball TX
Todd Deschepper - Spring TX
Jeffrey T. Wilson - Houston TX
Danny Higby - San Diego CA
Russ Wunderlich - Townwater WA

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1314

US Classification:

710129

Abstract:

A computer system includes a CPU and a memory device coupled by a North bridge logic unit to an expansion bus, such as a PCI bus. A South bridge logic connects to the expansion bus and couples various secondary busses and peripheral devices to the expansion bus. The South bridge logic includes internal control devices that are targets for masters on the expansion bus. The target devices couple to the expansion bus through a common expansion target interface, which monitors and translates master cycles on the expansion bus on behalf of the target devices. The South bridge also includes an internal modular target expansion bus coupling the internal target devices to the common target interface. The internal modular target expansion bus permits the target devices to receive master cycles from any expansion bus by understanding a standardized group of signals represented by the internal modular target expansion (IMAX) bus. The target interface then is responsible for understanding the protocol of the expansion bus and converting the expansion bus signals to IMAX target bus signals.

US Patent:

62267000, May 1, 2001

Filed:

Mar 13, 1998

Appl. No.:

9/042173

Inventors:

Shaun Wandler - Tomball TX
Jeffrey C. Stevens - Spring TX
Jeff W. Wolford - Spring TX
Robert Woods - Tomball TX
Danny Higby - San Diego CA
Russ Wunderlich - Turnwater WA
Todd Deschepper - Spring TX
Jeffrey T. Wilson - Houston TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1340
G06F 1336

US Classification:

710101

Abstract:

A computer system includes a CPU and a memory device coupled by a North bridge logic unit to an expansion bus, such as a PCI bus. A South bridge logic connects to the expansion bus and couples various secondary busses and peripheral devices to the expansion bus. The South bridge logic includes internal control devices or master devices that are designed to run master cycles on the expansion bus. The master devices couple to the expansion bus through a common expansion master interface, which executes master cycles on the expansion bus on behalf of the master devices. The South bridge also includes an internal modular master expansion bus coupling the internal master devices to the common master interface. The internal modular master expansion bus permits the master devices to run master cycles to any expansion bus by understanding a standardized group of signals represented by the internal modular master expansion (IMAX) bus. The master interface then is responsible for understanding the protocol of the expansion bus and converting the IMAX master bus signals to signals compatible with the expansion bus.

US Patent:

62633953, Jul 17, 2001

Filed:

Jan 6, 1999

Appl. No.:

9/227510

Inventors:

Patrick L. Ferguson - Cypress TX
Paul B. Rawlins - Spring TX
David F. Heinrich - Tomball TX
Robert L. Woods - Allentown PA

Assignee:

Compaq Computer Corp. - Houston TX

International Classification:

C06F 1314
C06F 948

US Classification:

710262

Abstract:

An interrupt controller may serially scan a plurality of interrupt request signals and/or receive interrupt request signals on parallel inputs. A scan latency may be associated with updating the status of serially scanned interrupt requests. Spurious interrupts may result from the scan latency. To reduce the chance of spurious interrupts, serially scanned interrupt requests may be masked for an amount of time following an end of interrupt (EOI). Write cycles to clear interrupt requests may be posted in a write buffer. The delay of such write cycles clearing the write buffer may also result in spurious interrupts. To reduce the chance of such spurious interrupts, EOI cycles may be delayed or retried until the write buffer empties.