Robert L Yin

US Patent:

6662285, Dec 9, 2003

Filed:

Jul 27, 2001

Appl. No.:

09/917304

Inventors:

Stephen M. Douglass - Saratoga CA
Prasad L. Sastry - Milpitas CA
Mehul R. Vashi - San Jose CA
Robert Yin - Castro Valley CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 1200

US Classification:

711167, 712 37, 713 1, 326 37

Abstract:

A data processing system having a user configurable memory controller, one or more local block RAMs, one or more global block RAMs and a processor core can be configured in a single field programmable gate array (FPGA). The address depth of the global block RAMs and the number of wait states can be selected by a user, and they can be set either prior to configuration of the FPGA or programmed using instructions of the processor core. The number of wait states of the local block RAM is also user selectable. An algorithm that can optimize the address depth and the number of wait states to achieve a performance level is also disclosed. The present invention can be applied to designs having separate instruction and data sides.

US Patent:

6976160, Dec 13, 2005

Filed:

Feb 22, 2002

Appl. No.:

10/082630

Inventors:

Robert Yin - Castro Valley CA, US
Mehul R. Vashi - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F001/24

US Classification:

713 1, 713 2, 713100, 716 16, 710 10, 710104, 326 38, 326 40, 326 46

Abstract:

During a reset condition or prior to system initialization of an FPGA-based system (), a FPGA () can be pre-configured by loading a value from a memory cell () into at least one flip-flop () of the FPGA, which represents a configuration register for an FPGA memory controller (). The FPGA memory controller can be configured using the value loaded in the flip-flop. The value loaded into the flip-flop from the memory cell can be a default value previously stored in the memory cell.

US Patent:

7085973, Aug 1, 2006

Filed:

Jul 9, 2002

Appl. No.:

10/192376

Inventors:

Robert Yin - Castro Valley CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G11C 29/00

US Classification:

714718

Abstract:

All the address lines in a data processing system can be tested by using one or more small memory device that do not occupy the full addressing capability of the address lines. In one embodiment, some of the address inputs of the memory device is connected to different address lines at different times. Instructions are pre-loaded into some locations of the memory device such that the address lines has to be asserted to fetch the instructions for execution. By executing the instructions and appropriately connecting the address lines to the address input, all the address lines can be tested. In another embodiment, some of the locations are pre-loaded with a set of predetermined values. A program then writes another set of predetermined values to associated locations. By reading the values in the locations and compared with the sets of predetermined values, it is possible to determine if the address lines are functioning properly.

US Patent:

7143218, Nov 28, 2006

Filed:

Jan 21, 2005

Appl. No.:

11/040135

Inventors:

Robert Yin - Castro Valley CA, US
Hamish T. Fallside - Los Gatos CA, US
Richard P. Burnley - Mountain View CA, US
Nicholas McKay - Edinburgh, GB
Martin B. Rhodes - Edinburgh, GB
Douglas M. Grant - Edinburgh, GB

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 13/14
H04L 12/28

US Classification:

710107, 3703953

Abstract:

Method and apparatus for address filtering for a media access controller is described. An application specific integrated circuit block) located in a programmable logic device includes a media access controller. The media access controller includes an address filter, which includes: address filter modules, a first logic tree coupled to each of the address filter modules and configured to provide a frame drop signal for delineation between a dropped frame and an address filtered frame; and a second logic tree coupled to each of the address filter modules to provide an address valid signal.

US Patent:

7197666, Mar 27, 2007

Filed:

Mar 21, 2003

Appl. No.:

10/393550

Inventors:

Robert Yin - Castro Valley CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 11/00

US Classification:

714 23, 714 10, 714 55

Abstract:

A method for checking the reset function of an embedded processor is described. First, a check is made to see if a reset “flag” is not set () before branching to execute the test routine that initiates the embedded processor's reset (). The test program sets the flag () before initiating the reset. When the processor resets and executes the test program from the beginning again, it determines that the flag was set (), and it does not execute the reset instructions again.

US Patent:

7315918, Jan 1, 2008

Filed:

Jan 14, 2005

Appl. No.:

11/035776

Inventors:

Robert Yin - Castro Valley CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 12/00

US Classification:

711104, 711125, 716 16

Abstract:

A programmable logic device having groups of data and instruction memory blocks separated by a processor block is described. The processor block including an embedded processor and data and instruction memory controllers. The data and instruction memory blocks respectively including data and memory groupings of block random access memories.

US Patent:

7330924, Feb 12, 2008

Filed:

Jan 21, 2005

Appl. No.:

11/040568

Inventors:

Ting Yun Kao - Cupertino CA, US
Robert Yin - Castro Valley CA, US
Hamish T. Fallside - Los Gatos CA, US
Richard P. Burnley - Mountain View CA, US
Nicholas McKay - Edinburgh, GB
Martin B. Rhodes - Edinburgh, GB
Stuart A. Nisbet - Edinburgh, GB
Gareth D. Edwards - Edinburgh, GB
Allan W. Fyfe - Edinburgh, GB

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H04L 12/66

US Classification:

710305, 710310, 710107, 370248, 370463, 370404, 370311, 370392, 370389, 370401, 370100, 709224, 709252, 713401, 713151

Abstract:

An aspect of the invention is physical layer interface for a network interface including a plurality of input/output pins. The input/output pins are coupled for being multiplexed into a physical layer interface selected from among a Reduced Gigabit Media Independent Interface and a Gigabit Media Independent Interface. The input/output pins internal to a programmable logic device are for access to and from a processor block located in the programmable logic device.

US Patent:

7366807, Apr 29, 2008

Filed:

Jan 21, 2005

Appl. No.:

11/040567

Inventors:

Robert Yin - Castro Valley CA, US
Hamish T. Fallside - Los Gatos CA, US
Richard P. Burnley - Mountain View CA, US
Nicholas McKay - Edinburgh, GB
Martin B. Rhodes - Edinburgh, GB
Douglas M. Grant - Edinburgh, GB
Stuart A. Nisbet - Edinburgh, GB
Gareth D. Edwards - Edinburgh, GB

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 13/00
H04L 12/00

US Classification:

710104, 370463

Abstract:

A statistics interface for a media access controller is described. The media access controller core includes a receive engine configured to provide a receive statistics vector associated with receive traffic. The receive engine is configured to output the receive statistics vector within an inter-frame gap over a number of receive clock cycles, where a portion of the receive statistics vector is provided with each clock cycle of the receive clock cycles.