Robin U Han

US Patent:

57512655, May 12, 1998

Filed:

May 16, 1995

Appl. No.:

8/442836

Inventors:

Robin Sungsoo Han - Saratoga CA

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G09G 336

US Classification:

345 88

Abstract:

A process for producing a wide range of shades in images that are presented in successive frames on image fields on opto-electronic display means having at least one illumination element at each of a plurality of pixel locations. Each pixel location, for example, may have a red, a green and a blue illumination element. The display is divided into uniformly-sized display neighborhoods. The process includes, for a given pixel location within any one of the uniformly-sized display neighborhoods, producing a given shade at that pixel location by selecting a frame sequence for illuminating the illumination elements at the pixel location during presentation of an image wherein the number of times that any given illumination element at the pixel location is illuminated within a given frame sequence is controlled to create an appearance of shading of that pixel location relative to other pixel locations and wherein adjacent pixel locations that have the same shade within any one of the display neighborhoods have their illumination elements illuminated with different frame sequences to minimize display noise.

US Patent:

56821700, Oct 28, 1997

Filed:

Jul 31, 1995

Appl. No.:

8/509651

Inventors:

Sridhar Kotha - Fremont CA
Alexander Eglit - San Carlos CA
Robin Han - Saratoga CA

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G09G 300
G09G 500

US Classification:

345 3

Abstract:

A method and apparatus for horizontally and vertically positioning a video graphics adapter (VGA) display image on the screen of a flat panel display (FPD) is provided with a first counter for setting a horizontal FPD disable period associated with the FPD. A second counter sets the horizontal FPD enable period of the FPD. This horizontal FPD enable period is greater than a composite horizontal pixel time of a VGA image to be displayed. A first circuit controls the start time of a subsequent horizontal FPD enable period. This start time is based on the horizontal FPD disable period. A second circuit controls the end time of the subsequent horizontal FPD enable period. This end time is based on the horizontal FPD enable period. The VGA display image is begun based on the start time of the subsequent horizontal FPD enable period to locate the VGA display image at a desired horizontal position of the FPD screen. The vertical positioning of the image is performed by similar counters and circuits.

US Patent:

57481636, May 5, 1998

Filed:

May 17, 1993

Appl. No.:

8/061804

Inventors:

Robin S. Han - Saratoga CA

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G09G 336

US Classification:

345 88

Abstract:

Shaded or color images are simulated using frame modulation techniques on flat panel displays having an array of binary display elements, i. e. , display elements that have only two display states, an ON state and an OFF state. The timing of ON/OFF and OFF/ON state transitions of picture elements within predetermined neighborhoods through the array of display elements is coordinated such that the state transitions occur substantially uniformly in space and time during a multi-frame display sequence. Using a multi-frame sequence 16 frames in duration, 16 shades of gray may be realized on a monochrome display. The number of shades may be increased to 64 using dynamic dithering. Dithering is applied by causing the multi-frame sequence to be 64 frames in duration and dividing the multi-frame sequence into four sub-sequences each 16 frames in duration with the duty cycle of each display element during each of the four 16-frame sub-sequences being allowed to assume one of two adjacent values only such that display noise is minimized. The method may be applied to color displays in which pixel locations have illumination elements each of a different color, for example a red illumination element, a green illumination element and a blue illumination element.

US Patent:

57573476, May 26, 1998

Filed:

May 17, 1993

Appl. No.:

8/061802

Inventors:

Robin S. Han - Saratoga CA

Assignee:

Cirrus Logtic, Inc. - Fremont CA

International Classification:

G09G 336

US Classification:

345 88

Abstract:

In a flat-panel display device, the ON/OFF duty cycle of each picture element of the array of picture elements is modulated during a multi-frame display sequence according to attribute information of respective picture element data to be displayed. The timing of ON/OFF and OFF/ON state transitions (i. e. , the modulations) of the picture elements are coordinated within predetermined neighborhoods throughout the array of picture elements such that the state transitions occur substantially uniformly in space and time within a display neighborhood during the multi-frame display sequence. Advantage is taken of the visual averaging property by causing state transitions to occur substantially uniformly in space and time within each neighborhood throughout the array of picture elements during a multi-frame display sequence. Individual state transitions, which by themselves constitute display noise, are not perceived; instead, a coherent pattern of state transitions blending is provided that effectively simulates non-monochrome image displays. Dithering techniques are applied to realize a greater number of display colors than would otherwise be possible using conventional color LCD displays.

US Patent:

58414185, Nov 24, 1998

Filed:

Jun 7, 1995

Appl. No.:

8/483584

Inventors:

Vald Bril - Campbell CA
Rakesh Bindlish - San Jose CA
Ken Fuiks - Fremont CA
Robin Sungsoo Han - Saratoga CA
Sridhar Kotha - Fremont CA
Alexander Julian Eglit - San Carlos CA

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G09G 500

US Classification:

345 3

Abstract:

A video controller for controlling at least two video displays having independent refresh rates and pixel resolutions. In a first embodiment, two separate data paths are provided within a video controller for each video display (e. g. , CRT and LCD). Taking advantage of the increased bandwidth of 64 bit wide DRAMS, data for each data path may be retrieved in separate read cycles. Each datapath may operate at its own clock frequency characteristic of refresh rate and pixel resolution. The dual data path embodiment also reduces the complexity of the software model needed to drive such dual displays. IN an alternative embodiment, a single data path may be provided within a video controller to drive data for two video displays having independent refresh rates and pixel resolutions. A data "tag" (extra bit) is attached to each word or dword passing through the data path indicating the destination (e. g. , CRT or LCD) of the video data.

US Patent:

57126577, Jan 27, 1998

Filed:

Mar 28, 1995

Appl. No.:

8/412158

Inventors:

Alexander Julian Eglit - San Carlos CA
Robin Sungsop Han - Saratoga CA

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G09G 510

US Classification:

345147

Abstract:

An adaptive dithering apparatus analyzes an input video signal as a function of available primary shades and produces a select signal whose value is a function of the desired shade represented by the input video signal and of the available primary shades. A combiner combines the input video signal with a selected one of a plurality of dither signals to generate a dithered input video signal. The one dither signal is selected under the control of the select signal. Finally, an adjustor receives the dithered input video signal, the available shade signal, and the select signal and, under the control of the select signal, adjusts the dithered input video signal to have a value equal to one of the available primary shades. Thus, an input video signal may be dithered with a dither signal that is optimized for dithering an input signal that falls into a particular range of desired shades. That is, a different dither signal may be employed for each possible spacing of adjacent available primary shades.

US Patent:

63105993, Oct 30, 2001

Filed:

Aug 28, 1996

Appl. No.:

8/704842

Inventors:

Vlad Bril - Campbell CA
Alexander Julian Eglit - Half Moon Bay CA
Robin Sungsoo Han - Saratoga CA
Muralidhar Reddy Jammula - Fremont CA

Assignee:

Cirrus Logic, Inc. - Austin TX

International Classification:

G09G 333

US Classification:

345 99

Abstract:

A flat panel display controller is provided with a circuit for monitoring clocking signal(s) to the flat panel display. A clocking signal output to the flat panel display may be fed back to the display controller using a conventional I/O pad. In the preferred embodiment, the fed back clocking signal resets a counter. In a second embodiment, the fed back clocking signal may then pass through an edge detector whose output then resets the counter. The counter will overflow if a edge signal is not received within a predetermined time period. If an overflow occurs, the carry signal of the counter will initiate a flat panel power shutdown through power control circuitry. The clock signal for the counter may be derived from an off-chip oscillator such that if a failure occurs within the display controller, the counter will continue to function.

US Patent:

60670711, May 23, 2000

Filed:

Jun 27, 1996

Appl. No.:

8/673793

Inventors:

Sridhar Kotha - Fremont CA
Vlad Bril - Campbell CA
Alexander J. Eglit - Half Moon Bay CA
Robin Sungsoo Han - Saratoga CA

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G09G 336

US Classification:

345132

Abstract:

A display controller in a computer system controls the output of graphics display data in a computer system having a fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a Discrete Time Oscillator (DTO) based clock divider and DCT based polyphase interpolation to upscale graphics display data from a first resolution to the panel resolution. DTO clock divider circuit synchronizes scan clocks between the input resolution and the desired output resolution. Within graphics display area, MVA. TM. display at greater color depth and resolution may be accommodated by additional DTO divider and interpolation steps.