Roderick Mason Miller

US Patent:

20150340319, Nov 26, 2015

Filed:

Aug 4, 2015

Appl. No.:

14/817546

Inventors:

- Grand Cayman, KY
O Sung Kwon - Wappingers Falls NY, US
Wen-Hu Hung - Mechanicville NY, US
Roderick Miller - Mechanicville NY, US
HongLiang Shen - Clifton Park NY, US

International Classification:

H01L 23/525

Abstract:

An e-fuse device disclosed herein includes an anode and a cathode that are conductively coupled to the doped region formed in a substrate, wherein the anode includes a first metal silicide region positioned on the doped region and a first conductive metal-containing contact that is positioned above and coupled to the first metal silicide region, and the cathode includes a second metal silicide region positioned on the doped region and a second conductive metal-containing contact that is positioned above and conductively coupled to the second metal silicide region. A method disclosed herein includes forming a doped region in a substrate for an e-fuse device and performing at least one common process operation to form a first conductive structure on the doped region of the e-fuse device and a second conductive structure on a source/drain region of a transistor.

US Patent:

20150179729, Jun 25, 2015

Filed:

Mar 5, 2015

Appl. No.:

14/639524

Inventors:

- Singapore, SG
Roderick MILLER - Mechanicville NY, US
Jie CHEN - Mechanicville NY, US

International Classification:

H01L 49/02
H01L 27/06

Abstract:

A method is provided for forming sandwich damascene resistors in MOL processes and the resulting devices. Embodiments include forming on a substrate a film stack including an interlayer dielectric (ILD), a first dielectric layer, and a sacrifice layer (SL); removing a portion of the SL and the first dielectric layer, forming a first cavity; conformally forming a layer of resistive material in the first cavity and over the SL; depositing a second dielectric layer over the layer of resistive material and filling the first cavity; and removing the second dielectric layer, the layer of resistive material not in the first cavity, and at least a partial depth of the SL

US Patent:

20150108580, Apr 23, 2015

Filed:

Dec 23, 2014

Appl. No.:

14/580834

Inventors:

- Grand Cayman, KY
Roderick Miller - Mechanicville NY, US
Marc Tarabbia - Pleasant Valley NY, US

International Classification:

H01L 27/06
H01L 29/08
H01L 29/735
H01L 29/78

US Classification:

257378

Abstract:

One method disclosed herein includes performing at least one common process operation to form a plurality of first gate structures for each of a plurality of field effect transistors and a plurality of second gate structures above a region where a bipolar transistor will be formed and performing an ion implantation process and a heating process to form a continuous doped emitter region that extends under all of the second gate structures. A device disclosed herein includes a first plurality of field effect transistors with first gate structures, a bipolar transistor that has an emitter region and a plurality of second gate structures positioned above the emitter region, wherein the bipolar transistor comprises a continuous doped emitter region that extends laterally under all of the plurality of second gate structures.

US Patent:

20150028447, Jan 29, 2015

Filed:

Jul 26, 2013

Appl. No.:

13/951654

Inventors:

- Grand Cayman, KY
O Sung Kwon - Wappingers Falls NY, US
Wen-Hu Hung - Mechanicville NY, US
Roderick Miller - Mechanicville NY, US
HongLiang Shen - Clifton Park NY, US

Assignee:

GLOBAL FOUNDRIES Inc. - Grand Cayman

International Classification:

H01L 23/525
H01L 21/768

US Classification:

257529, 438601

Abstract:

An e-fuse device disclosed herein includes an anode and a cathode that are conductively coupled to the doped region formed in a substrate, wherein the anode includes a first metal silicide region positioned on the doped region and a first conductive metal-containing contact that is positioned above and coupled to the first metal silicide region, and the cathode includes a second metal silicide region positioned on the doped region and a second conductive metal-containing contact that is positioned above and conductively coupled to the second metal silicide region. A method disclosed herein includes forming a doped region in a substrate for an e-fuse device and performing at least one common process operation to form a first conductive structure on the doped region of the e-fuse device and a second conductive structure on a source/drain region of a transistor.

US Patent:

20150001634, Jan 1, 2015

Filed:

Jun 28, 2013

Appl. No.:

13/930611

Inventors:

- Grand Cayman, KY
Roderick Miller - Mechanicville NY, US
Marc Tarabbia - Pleasant Valley NY, US

International Classification:

H01L 27/06
H01L 21/8249

US Classification:

257378, 438234

Abstract:

One method disclosed herein includes performing at least one common process operation to form a plurality of first gate structures for each of a plurality of field effect transistors and a plurality of second gate structures above a region where a bipolar transistor will be formed and performing an ion implantation process and a heating process to form a continuous doped emitter region that extends under all of the second gate structures. A device disclosed herein includes a first plurality of field effect transistors with first gate structures, a bipolar transistor that has an emitter region and a plurality of second gate structures positioned above the emitter region, wherein the bipolar transistor comprises a continuous doped emitter region that extends laterally under all of the plurality of second gate structures.

US Patent:

20140231960, Aug 21, 2014

Filed:

Feb 15, 2013

Appl. No.:

13/767930

Inventors:

- Grand Cayman, KY
Roderick M. Miller - Mechanicville NY, US
Shesh M. Pandey - Clifton Park NY, US
Jagar Singh - Clifton Park NY, US

Assignee:

GLOBALFOUNDRIES INC. - Grand Cayman

International Classification:

H01L 49/02

US Classification:

257536, 438385

Abstract:

Aspects of the present invention relate to an approach for implanting and forming a polysilicon resistor with a single implant dose. Specifically, a mask having a set of openings is formed over a resistor surface. The set of openings are typically formed in a column-row arrangement according to a predetermined pattern. Forming the mask in this manner allows the resistor surface to have multiple regions/zones. A first region is defined by the set of openings in the mask, and a second region is defined by the remaining portions of the mask. The resistor is then subjected to a single implant dose via the openings. Implanting the resistor in this manner allows the resistor to have multiple resistance values (i.e., a first resistance value in the first region, and a second resistance value in the second region).

US Patent:

20140191367, Jul 10, 2014

Filed:

Jan 10, 2013

Appl. No.:

13/738604

Inventors:

- Singapore, SG
Roderick Miller - Mechanicville NY, US
Jie Chen - Mechanicville NY, US

Assignee:

GLOBALFOUNDRIES SINGAPORE PTE. LTD. - Singapore

International Classification:

H01L 49/02

US Classification:

257537, 438382

Abstract:

A method is provided for forming sandwich damascene resistors in MOL processes and the resulting devices. Embodiments include forming on a substrate a film stack including an interlayer dielectric (ILD), a first dielectric layer, and a sacrifice layer (SL); removing a portion of the SL and the first dielectric layer, forming a first cavity; conformally forming a layer of resistive material in the first cavity and over the SL; depositing a second dielectric layer over the layer of resistive material and filling the first cavity; and removing the second dielectric layer, the layer of resistive material not in the first cavity, and at least a partial depth of the SL.