Roger Lee Howe

US Patent:

6448622, Sep 10, 2002

Filed:

Jul 17, 2000

Appl. No.:

09/617300

Inventors:

Andrea Franke - Oakland CA
Roger T. Howe - Martinez CA

Assignee:

The Regents of the University of California - Berkeley CA

International Classification:

H01L 2982

US Classification:

257415, 257414, 257616, 438 50, 438 53

Abstract:

This invention relates to micro-electromechanical systems using silicon-germanium films. Such a system includes one or more layers of Si Ge , deposited on a substrate, where 0x1. One or more transistors can be formed on the substrate.

US Patent:

7514853, Apr 7, 2009

Filed:

May 10, 2007

Appl. No.:

11/801774

Inventors:

Roger T. Howe - Los Gatos CA, US
Emmanuel P. Quevy - El Cerrito CA, US
David H. Bernstein - Oakland CA, US

Assignee:

Silicon Clocks, Inc. - Fremont CA

International Classification:

H01L 23/34

US Classification:

310346, 310328, 310315, 310338

Abstract:

A MEMS structure having a temperature-compensated resonating member is described. The MEMS structure comprises a stress inverter member coupled with a substrate. A resonating member is housed in the stress inverter member and is suspended above the substrate. The MEMS stress inverter member is used to alter the thermal coefficient of frequency of the resonating member by inducing a stress on the resonating member in response to a change in temperature.

US Patent:

7591201, Sep 22, 2009

Filed:

Mar 9, 2007

Appl. No.:

11/716285

Inventors:

David H. Bernstein - Oakland CA, US
Roger T. Howe - Los Gatos CA, US
Emmanuel P. Quevy - El Cerrito CA, US

Assignee:

Silicon Clocks, Inc. - Fremont CA

International Classification:

F16H 33/14

US Classification:

74 32, 74 2

Abstract:

A MEMS structure having a compensated resonating member is described. In an embodiment, a MEMS structure comprises a resonating member coupled to a substrate by an anchor. A dynamic mass-load is coupled with the resonating member. The dynamic mass-load is provided for compensating a change in frequency of the resonating member by altering the moment of inertia of the resonating member by way of a positional change relative to the anchor.

US Patent:

7595209, Sep 29, 2009

Filed:

Mar 9, 2007

Appl. No.:

11/716233

Inventors:

Pezhman Monadgemi - Fremont CA, US
Emmanuel P. Quevy - El Cerrito CA, US
Roger T. Howe - Los Gatos CA, US

Assignee:

Silicon Clocks, Inc. - Fremont CA

International Classification:

H01L 21/56
H01L 21/50

US Classification:

438 51, 438 48, 438 50, 438127, 257E21499, 257E29324

Abstract:

Multi-layered, planar microshells having low stress for encapsulation of devices such as MEMS and microelectronics. The microshells may include a perforated pre-sealing layer, below which a sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. The sealing layer may further include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation. The various layers may be formed employing processes having opposing stresses to tune the residual stress of the multi-layered microshell. In an embodiment, the hermetic layer is a metal which is deposited with a process tuned to impart a tensile stress to lower the residual stress in the microshell below the magnitude of cumulative stress present in sealing layer and pre-sealing layer.

US Patent:

7659150, Feb 9, 2010

Filed:

Mar 9, 2007

Appl. No.:

11/716156

Inventors:

Pezhman Monadgemi - Fremont CA, US
Roger T. Howe - Los Gatos CA, US
Emmanuel P. Quevy - El Cerrito CA, US

Assignee:

Silicon Clocks, Inc. - Fremont CA

International Classification:

H01L 21/00

US Classification:

438125, 257E23193

Abstract:

Microshells for encapsulation of devices such as MEMS and microelectronics. In an embodiment, the microshells include a planar perforated pre-sealing layer, below which a non-planar sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. The sealing layer may include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation as a function of the dimension of the perforation to form cavities having different vacuum levels on the same substrate.

US Patent:

7736929, Jun 15, 2010

Filed:

Mar 9, 2007

Appl. No.:

11/716422

Inventors:

Pezhman Monadgemi - Fremont CA, US
Emmanuel P. Quevy - El Cerrito CA, US
Roger T. Howe - Los Gatos CA, US

Assignee:

Silicon Clocks, Inc. - Fremont CA

International Classification:

H01L 21/00
H01L 21/461
H01L 21/50
C23F 1/00
C25F 3/00

US Classification:

438 51, 438 48, 438690, 257E21499, 216 2, 216 11

Abstract:

Low temperature, multi-layered microshells for encapsulation of devices such as MEMS and microelectronics. The microshells may include a perforated pre-sealing layer, below which a sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. The pre-sealing layer includes a large surface area getter layer to remove contaminants from the space ultimately enclosed by the microshell to improve the pressure control and cleanliness of the microshell.

US Patent:

7956517, Jun 7, 2011

Filed:

Sep 4, 2008

Appl. No.:

12/204713

Inventors:

Mehrnaz Motiee - Fremont CA, US
Roger T. Howe - Los Gatos CA, US
Emmanuel P. Quevy - El Cerrito CA, US
David H. Bernstein - San Francisco CA, US

Assignee:

Silicon Laboratories - Austin TX

International Classification:

H01L 23/34

US Classification:

310346, 310315, 310341, 310367, 310368, 310321

Abstract:

A MEMS structure having a temperature-compensated resonator member is described. The MEMS structure comprises an asymmetric stress inverter member coupled with a substrate. A resonator member is housed in the asymmetric stress inverter member and is suspended above the substrate. The asymmetric stress inverter member is used to alter the thermal coefficient of frequency of the resonator member by inducing a stress on the resonator member in response to a change in temperature.

US Patent:

8633573, Jan 21, 2014

Filed:

Feb 16, 2010

Appl. No.:

12/706112

Inventors:

Jinendra Raja Jain - Stanford CA, US
Roger T. Howe - Stanford CA, US

Assignee:

The Board of Trustees of the Leland Stanford Junior University - Palo Alto CA

International Classification:

H01L 29/06

US Classification:

257629, 257 18, 257 19, 257E29006, 257E21211, 438478, 438703, 438763

Abstract:

Various applications are directed to a material stack having a strained active material therein. In connection with an embodiment, an active material (e. g. a semiconductor material) is at least initially and partially released from and suspended over a substrate, strained, and held in place. The release and suspension facilitates the application of strain to the semiconductor material.