Roger Hy Howe

US Patent:

6448622, Sep 10, 2002

Filed:

Jul 17, 2000

Appl. No.:

09/617300

Inventors:

Andrea Franke - Oakland CA
Roger T. Howe - Martinez CA

Assignee:

The Regents of the University of California - Berkeley CA

International Classification:

H01L 2982

US Classification:

257415, 257414, 257616, 438 50, 438 53

Abstract:

This invention relates to micro-electromechanical systems using silicon-germanium films. Such a system includes one or more layers of Si Ge , deposited on a substrate, where 0x1. One or more transistors can be formed on the substrate.

US Patent:

6478974, Nov 12, 2002

Filed:

Jul 6, 1999

Appl. No.:

09/347903

Inventors:

Kyle S. Lebouitz - Albany CA
Roger T. Howe - Lafayette CA
Albert P. Pisano - Livermore CA

Assignee:

The Regents of the University of California - Oakland CA

International Classification:

B01D 6700

US Classification:

216 2, 216 39, 216 56, 216 97

Abstract:

A method of fabricating a microfabricated filter. The method includes forming a frame structure and forming a plurality of openings through the frame structure. A permeable polysilicon membrane is formed over the plurality of openings through the frame structure. At least part of the sacrificial structure is etched with an etchant wherein the etchant passes through the permeable polysilicon membrane. The permeable polycrystal silicon membrane may have a thickness of between about 0. 05 micrometers and about 0. 30 micrometers.

US Patent:

7151277, Dec 19, 2006

Filed:

Jul 3, 2003

Appl. No.:

10/613508

Inventors:

Di Gao - Albany CA, US
Roger T. Howe - Martinez CA, US
Roya Maboudian - Orinda CA, US

Assignee:

The Regents of the University of California - Oakland CA

International Classification:

H01L 29/04
H01L 29/76
H01L 29/26
H01L 31/12
H01L 33/00

US Classification:

257 51, 257 67, 257 72, 257 79

Abstract:

A method of etching silicon carbide using a nonmetallic mask layer. The method includes providing a silicon carbide substrate; forming a non-metallic mask layer by applying a layer of material on the substrate; patterning the mask layer to expose underlying areas of the substrate; and etching the underlying areas of the substrate with a plasma at a first rate, while etching the mask layer at a rate lower than the first rate.

US Patent:

7211926, May 1, 2007

Filed:

Feb 23, 2006

Appl. No.:

11/361814

Inventors:

Emmanuel P. Quevy - El Cerrito CA, US
Roger T. Howe - Los Gatos CA, US

Assignee:

The Regents of the University of California - Oakland CA

International Classification:

H03B 28/00
H03B 5/04

US Classification:

310315, 310309, 331 66, 331 69, 331108 D, 331155, 331156, 331177 R

Abstract:

Disclosed is an oscillator that relies on redundancy of similar resonators integrated on chip in order to fulfill the requirement of one single quartz resonator. The immediate benefit of that approach compared to quartz technology is the monolithic integration of the reference signal function, implying smaller devices as well as cost and power savings.

US Patent:

7256107, Aug 14, 2007

Filed:

May 3, 2005

Appl. No.:

11/121690

Inventors:

Hideki Takeuchi - El Cerrito CA, US
Emmanuel P. Quevy - Berkeley CA, US
Roger T. Howe - Martinez CA, US

Assignee:

The Regents of the University of California - Oakland CA

International Classification:

H01L 21/46
H01L 21/78
H01L 21/301

US Classification:

438460, 438113, 438933, 257E21017, 257E21127, 257E21229, 257E21237, 257E21304

Abstract:

In fabricating a microelectromechanical structure (MEMS), a method of forming a narrow gap in the MEMS includes a) depositing a layer of sacrificial material on the surface of a supporting substrate, b) photoresist masking and at least partially etching the sacrificial material to form at least one blade of sacrificial material, c) depositing a structural layer over the sacrificial layer, and d) removing the sacrificial layer including the blade of the sacrificial material with a narrow gap remaining in the structural layer where the blade of sacrificial material was removed.

US Patent:

7591201, Sep 22, 2009

Filed:

Mar 9, 2007

Appl. No.:

11/716285

Inventors:

David H. Bernstein - Oakland CA, US
Roger T. Howe - Los Gatos CA, US
Emmanuel P. Quevy - El Cerrito CA, US

Assignee:

Silicon Clocks, Inc. - Fremont CA

International Classification:

F16H 33/14

US Classification:

74 32, 74 2

Abstract:

A MEMS structure having a compensated resonating member is described. In an embodiment, a MEMS structure comprises a resonating member coupled to a substrate by an anchor. A dynamic mass-load is coupled with the resonating member. The dynamic mass-load is provided for compensating a change in frequency of the resonating member by altering the moment of inertia of the resonating member by way of a positional change relative to the anchor.

US Patent:

7595209, Sep 29, 2009

Filed:

Mar 9, 2007

Appl. No.:

11/716233

Inventors:

Pezhman Monadgemi - Fremont CA, US
Emmanuel P. Quevy - El Cerrito CA, US
Roger T. Howe - Los Gatos CA, US

Assignee:

Silicon Clocks, Inc. - Fremont CA

International Classification:

H01L 21/56
H01L 21/50

US Classification:

438 51, 438 48, 438 50, 438127, 257E21499, 257E29324

Abstract:

Multi-layered, planar microshells having low stress for encapsulation of devices such as MEMS and microelectronics. The microshells may include a perforated pre-sealing layer, below which a sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. The sealing layer may further include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation. The various layers may be formed employing processes having opposing stresses to tune the residual stress of the multi-layered microshell. In an embodiment, the hermetic layer is a metal which is deposited with a process tuned to impart a tensile stress to lower the residual stress in the microshell below the magnitude of cumulative stress present in sealing layer and pre-sealing layer.

US Patent:

7659150, Feb 9, 2010

Filed:

Mar 9, 2007

Appl. No.:

11/716156

Inventors:

Pezhman Monadgemi - Fremont CA, US
Roger T. Howe - Los Gatos CA, US
Emmanuel P. Quevy - El Cerrito CA, US

Assignee:

Silicon Clocks, Inc. - Fremont CA

International Classification:

H01L 21/00

US Classification:

438125, 257E23193

Abstract:

Microshells for encapsulation of devices such as MEMS and microelectronics. In an embodiment, the microshells include a planar perforated pre-sealing layer, below which a non-planar sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. The sealing layer may include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation as a function of the dimension of the perforation to form cavities having different vacuum levels on the same substrate.