Roger I Kung

US Patent:

42674662, May 12, 1981

Filed:

Mar 5, 1979

Appl. No.:

6/017746

Inventors:

Roger I. Kung - Austin TX
Jerry D. Moench - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 326

US Classification:

307279

Abstract:

A signal generating circuit is provided which provides an output signal in response to an input signal. The output signal has minimum delay with respect to the input signal. The signal generating circuit has an inverter to receive the input signal. A cross coupled latch is coupled to the inverter and provides the output signal. A DC load stage is used as a load for the cross coupled latch. A transistor is coupled to the output signal to pull the output signal low upon command. Control circuitry is coupled to the transistor and helps precondition the signal generating circuitry so that it can respond to the input signal with minimum delay.

US Patent:

42020450, May 6, 1980

Filed:

Mar 5, 1979

Appl. No.:

6/017747

Inventors:

Roger I. Kung - Austin TX
Jerry D. Moench - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G11C 1300

US Classification:

365203

Abstract:

There is provided a write circuit which is held in a disabled state until data is available to be written into the memory. This circuit is particularly useful for memories having one data in buffer and more than one memory block wherein each memory block has a write circuit to couple data in from the data in buffer. The write circuit has an input transfer device which is maintained in a disabled condition by an address signal until it is addressed. The output of the transfer device is maintained in a discharged state by the complement of the column address strobe. The output of the transfer device is coupled by a latch circuit to bit sense common lines in the memory.

US Patent:

54023890, Mar 28, 1995

Filed:

Mar 8, 1994

Appl. No.:

8/207513

Inventors:

Stephen T. Flannagan - Austin TX
Kenneth W. Jones - Austin TX
Roger I. Kung - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G11C 800

US Classification:

365233

Abstract:

A synchronous memory (20) has parallel data output registers (34) and a dummy path (46). The output data from a memory array (22) is provided to the parallel output registers (34). The output registers (34) provide two parallel, interleaved, output data paths. The data in each path changes every other cycle of a clock signal. Dummy path (46) contains delay elements that model a propagation delay for a data path of the memory (20) during a read cycle. Using parallel data output registers (34) increases a time in which data is valid during the read cycle. The dummy path (46) tracks the output data signal in terms of process, power supply and temperature variations to ensure that the correct data is acquired during the read cycle.

US Patent:

42504120, Feb 10, 1981

Filed:

Mar 5, 1979

Appl. No.:

6/017748

Inventors:

Roger I. Kung - Austin TX
Jerry D. Moench - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 326
H03K 522

US Classification:

307279

Abstract:

There is provided a dynamic output buffer useful for providing output data from a memory. The output buffer includes a cross coupled sense amplifier having inputs and outputs. The outputs of this sense amplifier are coupled by output transistors to the output of the dynamic output buffer. The outputs of the cross coupled sense amplifier are also coupled to dynamic load devices which are used to prevent the outputs from deteriorating when the inputs are shunted or clamped to ground. The inputs are clamped to ground by transistors which are controlled by timing signals and thereby insure that data stored by the cross coupled sense amplifier will not be lost.