Roger B Pierson

Address:

164 Bunker Hl Ln, Castleton, VA 22716

VIN:

JTDJT923375119830

Make:

TOYOTA

Model:

YARIS

Year:

2007

US Patent:

6496593, Dec 17, 2002

Filed:

May 5, 1999

Appl. No.:

09/305306

Inventors:

Duane A. Burchick - Fort Washington MD
Roger B. Pierson - Castleton VA
Mehmet C. Ertem - McLean VA
Thomas J. Ippolito - Potomac MD

Assignee:

University Research Foundation, Inc. - Greenbelt MD

International Classification:

G06K 900

US Classification:

382104, 340540

Abstract:

A system for remote detection of muzzle blasts produced by rifles, artillery and other weapons, and similar explosive events. The system includes an infrared camera, image processing circuits, targeting computation circuits, displays, user interface devices, weapon aim point measurement devices, confirmation sensors, target designation devices and counterfire weapons. The camera is coupled to the image processing circuits. The image processing circuits are coupled to the targeting location computation circuits. The aim point measurement devices are coupled to the target computation processor. The system includes visual target confirmation sensors which are coupled to the targeting computation circuits.

US Patent:

58419748, Nov 24, 1998

Filed:

Mar 18, 1996

Appl. No.:

8/617051

Inventors:

Norris Krone - Annandale VA
Roger Pierson - Castleton VA
Glenn Connor - Laurel MD
Virgil Davis - Fulton MD

Assignee:

University Research Foundation, Inc. - Greenbelt MD

International Classification:

G06F 1338
H04J 302

US Classification:

39520031

Abstract:

A high speed data collection processing and distribution system for coupling a plurality of digital data sources to a plurality of digital data processors. The system includes a plurality of segmented parallel data paths and a plurality of nodes connecting said parallel data paths in an endless ring. Each node includes an input connector for connecting the end of one of said segments of parallel data paths on a one-for-one basis; a data multiplexer, a plurality of node parallel data paths in the node corresponding to the segmented parallel data paths, respectively, connected to the input connector and the data multiplexer such that data input to the multiplexer corresponds to respective ones of the segmented parallel data paths. A processor is coupled to said node parallel data paths, and as a second input to the multiplexer a common source of clock and slot signals is independently connected to said control processor in each node, respectively, for controlling the timing thereof. Each node also includes transmit and receive FIFO buffer memories, address, exclusive source and pattern match circuits and a local clock distribution circuit.

US Patent:

55028179, Mar 26, 1996

Filed:

Apr 2, 1993

Appl. No.:

8/042273

Inventors:

Norris Krone - Annandale VA
Roger Pierson - Castleton VA
Glenn Connor - Laurel MD
Virgil Davis - Fulton MD

Assignee:

University Research Foundation, Inc. - Greenbelt MD

International Classification:

G06F 1338
H04J 302

US Classification:

39520016

Abstract:

A high speed data collection processing and distribution system for coupling a plurality of digital data sources to a plurality of digital data processors. The system includes a plurality of segmented parallel data paths and a plurality of nodes connecting said parallel data paths in an endless ring. Each node includes an input connector for connecting the end of one of said segments of parallel data paths on a one-for-one basis; a data multiplexer, a plurality of node parallel data paths in the node corresponding to the segmented parallel data paths, respectively, connected to the input connector and the data multiplexer such that data input to the multiplexer corresponds to respective ones of the segmented parallel data paths. A processor is coupled to said node parallel data paths, and as a second input to the multiplexer a common source of clock and slot signals is independently connected to said control processor in each node, respectively, for controlling the timing thereof. Each node also includes transmit and receive FIFO buffer memories, address, exclusive source and pattern match circuits and a local clock distribution circuit.