Roger G Rolbiecki from 4853 Countryside Dr, Saint Paul, MN 55126, age 71, Phone: 6127701810

Resumes

Consultant At Gosemis Llc

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Position:

Consultant at GoSemis LLC

Location:

Greater Minneapolis-St. Paul Area

Industry:

Design

Work:

GoSemis LLC since May 2009
Consultant
Seagate Technology Apr 2007 - May 2009
Prin. Design Eng
SiliconLogic Engineering 2004 - 2006
Senior Eng
Guidant 1992 - 2004
Prin Eng
Cypress Semiconductor 1990 - 1992
Prin Yield Enhancement Eng

Education:

Ohio University 1976 - 1978
MS, PhysicsBA Math 1976 BA Physics 1976 Winona State University Winona,MN

Us Patents

Mirrored-Gate Cell For Non-Volatile Memory
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US Patent:

8053749, Nov 8, 2011
Filed:

Feb 20, 2009
Appl. No.:

12/389817
Inventors:

Roger Glenn Rolbiecki - Shoreview MN, US
Andrew Carter - Minneapolis MN, US
Yong Lu - Rosemount MN, US
Assignee:

Seagate Technology LLC - Scotts Valley CA
International Classification:

H01L 47/00
US Classification:

257 2, 257 3, 257 4, 257316
Abstract:

A memory comprising at least one memory cell operationally connected to a bit line, a source line and a word line. The memory cell comprises a substrate having a first source contact, a second source contact, and a bit contact between the first source contact and the second source contact, a first transistor gate electrically connecting the first source contact and the bit contact and a second transistor gate electrically connecting the bit contact and the second source contact. The word line electrically connects the first transistor gate to the second transistor gate.

Mirrored-Gate Cell For Non-Volatile Memory
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US Patent:

8324607, Dec 4, 2012
Filed:

Oct 25, 2011
Appl. No.:

13/280392
Inventors:

Roger Glenn Rolbiecki - Shoreview MN, US
Andrew Carter - Minneapolis MN, US
Yong Lu - Rosemount MN, US
Assignee:

Seagate Technology LLC - Scotts Valley CA
International Classification:

H01L 47/00
US Classification:

257 2, 257 3, 257 4
Abstract:

A memory comprising at least one memory cell operationally connected to a bit line, a source line and a word line. The memory cell comprises a substrate having a first source contact, a second source contact, and a bit contact between the first source contact and the second source contact, a first transistor gate electrically connecting the first source contact and the bit contact and a second transistor gate electrically connecting the bit contact and the second source contact. The word line electrically connects the first transistor gate to the second transistor gate.

Non-Volatile Memory Cell With Multiple Resistive Sense Elements Sharing A Common Switching Device
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US Patent:

20100118589, May 13, 2010
Filed:

Apr 15, 2009
Appl. No.:

12/424065
Inventors:

Andrew John Carter - Minneapolis MN, US
Maroun Georges Khoury - Burnsville MN, US
Yong Lu - Edina MN, US
Roger Glenn Rolbiecki - Shoreview MN, US
Assignee:

SEAGATE TECHNOLOGY LLC - Scotts Valley CA
International Classification:

G11C 11/00
G11C 7/00
G11C 11/14
US Classification:

365148, 365189011, 365171, 365163
Abstract:

A non-volatile memory cell array and associated method of use are disclosed. In accordance with various embodiments, the array includes a plurality of programmable resistive sense elements (RSEs) coupled to a shared switching device. The switching device has a common source region and multiple drain regions, each drain region connected to an associated RSE from said plurality of RSEs.

Non-Volatile Memory Cell With Multiple Resistive Sense Elements Sharing A Common Switching Device
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US Patent:

20110149639, Jun 23, 2011
Filed:

Mar 1, 2011
Appl. No.:

13/037955
Inventors:

Andrew John Carter - Minneapolis MN, US
Maroun Georges Khoury - Burnsville MN, US
Yong Lu - Edina MN, US
Roger Glenn Rolbiecki - Shoreview MN, US
Assignee:

SEAGATE TECHNOLOGY LLC - Scotts Valley CA
International Classification:

G11C 11/00
H01L 45/00
US Classification:

365148, 257 2, 257E45001
Abstract:

A non-volatile memory cell array and associated method of use. In accordance with various embodiments, the array includes a plurality of programmable resistive sense elements (RSEs) coupled to a shared switching device. The switching device has a common source region and multiple drain regions, each drain region connected to an associated RSE from said plurality of RSEs.