Alon Naveh - Ramat Hasharon, IL Roman Surgutchik - Santa Clara CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/26 G06F 1/28
US Classification:
713300, 713322
Abstract:
An apparatus to determine if a temperature of an electronic device is equal to or exceeds a predetermined threshold. In response to detecting the temperature of the electronic device has at least reached the predetermined threshold, determining a target throttling point for a processor, the target throttling point including a target operating frequency and target operating voltage. Thereafter, dynamically changing a current operating point for the electronic device including a current operating frequency and a current operating voltage by non-contemporaneously changing the current operating frequency to the target operating frequency and the current operating voltage to the target operating voltage. During the changing of the current operating voltage the device is in an active state.
Method And System For Memory Temperature Detection And Thermal Load Management
David G. Reed - Saratoga CA, US Brad W. Simeral - San Francisco CA, US Roman Surgutchik - Santa Clara CA, US Joshua Titus - Sunnyvale CA, US
Assignee:
Nvidia Corporation - Santa Clara CA
International Classification:
G01K 1/00 G01K 3/00 G01K 5/00 G01K 7/00 G01K 9/00
US Classification:
702130, 374100, 711104, 711105, 711106
Abstract:
A method and system for memory temperature measurement. The method includes the step of monitoring a plurality of accesses to a memory component. A number of accesses occurring to the memory component over a time period is determined. A temperature of the memory component is determined based on the number of accesses occurring over the time period.
Method And Apparatus To Dynamically Change An Operating Frequency And Operating Voltage Of An Electronic Device
Alon Naveh - Ramat Hasharon, IL Roman Surgutchik - Santa Clara CA, US Stephen H. Gunther - Beaverton OR, US Robert Greiner - Beaverton OR, US Kevin Dai - San Jose CA, US Keng L. Wong - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/00 H03B 19/00
US Classification:
713322, 713320, 327113
Abstract:
In one embodiment, there is provided a method comprising determining a target operating point for an electronic device, the target operating point including a target operating frequency and a target operating voltage; and dynamically changing a current operating point for the electronic device including a current operating frequency and a current operating voltage by non-contemporaneously changing the current operating frequency to the target operating frequency and a current operating voltage to the target operating voltage, wherein during the changing the electronic device is in an active state.
System, Apparatus And Method For Reclaiming Memory Holes In Memory Composed Of Arbitrarily-Sized Memory Devices
Sean Jeffrey Treichler - Mountain View CA, US Brad W. Simeral - San Franciso CA, US David G. Reed - Saratoga CA, US Roman Surgutchik - Santa Clara CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 9/26 G06F 9/34 G06F 12/00
US Classification:
711203, 711202, 711220, 711165
Abstract:
A system, apparatus, and method are disclosed for increasing the physical memory address space accessible to a processor, at least in part, by translating linear addresses associated with a memory hole into a subset of physical memory addresses that otherwise is inaccessible as system memory by a processor. In one embodiment, a memory controller reclaims memory holes in a system memory divided into ranges of linear addresses, where the system memory includes a number of arbitrarily-sized memory devices. The memory controller includes a memory configuration evaluator configured to determine a translated memory hole size for a memory hole, the memory hole including restricted linear addresses that translate into a subset of physical addresses. Also, memory configuration evaluator can be configured to form adjusted ranges to translate at least one linear address into a subset of physical addresses. As such, the system memory increases by at least the subset of physical addresses.
System, Apparatus And Method For Reclaiming Memory Holes In Memory Composed Of Identically-Sized Memory Devices
Brad W. Simeral - San Francisco CA, US Sean Jeffrey Treichler - Mountain View CA, US David G. Reed - Saratoga CA, US Roman Surgutchik - Santa Clara CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 9/26 G06F 9/34 G06F 12/00
US Classification:
711202, 711200
Abstract:
A system, apparatus, and method are disclosed for increasing the physical memory size accessible to a processor, at least in part, by reclaiming physical address space typically associated with addresses of a restricted linear address space (i. e. , addresses that are otherwise unusable by the processor as system memory). In one embodiment, an exemplary memory controller redirects a linear address associated with a range of addresses to access a reclaimed memory hole. The memory controller includes an address translator configured to determine an amount of restricted addresses and to establish a baseline address identified as a first number being a first integer power of 2. The range of addresses can be located at another address identified as a second number being a second integer power of 2. As such, the address translator translates the linear address into a translated address associated with the reclaimed memory hole based on the baseline address.
Method And System For Memory Thermal Load Sharing Using Memory On Die Termination
David G. Reed - Saratoga CA, US Brad W. Simeral - San Francisco CA, US Roman Surgutchik - Santa Clara CA, US Joshua Titus - Sunnyvale CA, US
Assignee:
Nvidia Corporation - Santa Clara CA
International Classification:
G11C 7/04
US Classification:
365211, 365212, 326 30
Abstract:
Memory component temperature information is used to implement a method for ODT (on die termination) thermal load management. A respective temperature of a plurality of memory components are accessed, and based on this temperature, an ODT cycle is directed to a first of the memory components to avoid imposing a thermal load from the ODT cycle on a second of the memory components.
Network Interface Speed Adjustment To Accommodate High System Latency In Power Savings Mode
A system is coupled to a network by a network interface. In a power savings mode the speed setting of the network interface is reduced to accommodate increased system latency.
Apparatus, Method, And System For Dynamically Selecting Power Down Level
Roman Surgutchik - Santa Clara CA, US Robert William Chapman - Mountain View CA, US Edward L. Riegelsberger - Fremont CA, US Brad W. Simeral - San Francisco CA, US Paul J. Gyugyi - Sunnyvale CA, US
Assignee:
Nvidia Corporation - Santa Clara CA
International Classification:
G06F 1/26
US Classification:
713321, 713323, 713324
Abstract:
A system has a plurality of different clients. Each client generates a report signal indicative of a current latency tolerance associated with a performance state. A controller dynamically determines a power down level having a minimum power consumption capable of supporting the system latency of the configuration state of the clients.