Ronald A Cooper

US Patent:

47165235, Dec 29, 1987

Filed:

Jun 14, 1985

Appl. No.:

6/744852

Inventors:

Gilbert S. Burrus - Apex NC
Ronald J. Cooper - Raleigh NC
Michael R. Marr - Chapel Hill NC
John C. Pescatore - Chapel Hill NC
Mario A. Marsico - Cary NC

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1332

US Classification:

364200

Abstract:

Both DMA access and character interrupt driven access modes of service are provided to multiple communication ports by an integrated arbitration DMA/interrupt controller utilizing its own resident randomly accessible memory. Pipelined logic control architecture for handling service mode adaptations for each individual port and for managing memory accesses to main system memory enables the use of the random access memory with its inherent time delays in a manner that virtually eliminates the effect of any time delay in overall memory access throughput.

US Patent:

61755567, Jan 16, 2001

Filed:

Jan 6, 1997

Appl. No.:

8/779726

Inventors:

James Johnson Allen - Raleigh NC
Ronald Julius Cooper - Raleigh NC

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04J 302

US Classification:

370293

Abstract:

A system and method for remotely powering an Ethernet network repeater through an attachment unit interface (AUI) between the repeater and a remote personal computer ("PC") or workstation. The AUI includes logic circuitry to detect when the Ethernet is supporting a transmit signal and a receive signal. Associated with the AUI is a DC to DC converter which receives, remotely through the AUI interface, a DC voltage from the PC or workstation and converts the DC voltage into working voltages for the remote repeater.

US Patent:

46270540, Dec 2, 1986

Filed:

Aug 27, 1984

Appl. No.:

6/644888

Inventors:

Ronald J. Cooper - Raleigh NC
Mario A. Marsico - Cary NC
John C. Pescatore - Durham NC

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1100

US Classification:

371 11

Abstract:

A multiprocessor array is described in which a central controlling microprocessor interfaces over commonly connected address and data busses to a plurality of peripheral microprocessors. A memory mapped I/O interface controls access to and from the busses for mutual receipt and exchange of signals between the processors and mutual exchange and receipt of data among the processors. The individual processors are selectively isolatable by a plurality of three state switch means connected between each processor and the interconnecting data and address busses. Error detection and control logic is connected via control lines to the individual processors and responsive to an error indication thereof, activates a multipoint error signal to all said microprocessors over a control line, which signal is interpreted by the processor then controlling said busses as a signal to deactivate its operation and as a signal at said control microprocessor to invoke an interrupt for analyzing the causes of said error. The control microprocessor can issue memory mapped I/O instructions to the individual three state selective isolation means and/or to any of the I/O microprocessors to respectively isolate the processors from said busses or to control said processors in an error analysis routine. The apparatus further includes a machine check register and a bus master register associated with said control microprocessor which registers can be written in by said control microprocessor and read from only by one of said I/O microprocessors.

US Patent:

47516348, Jun 14, 1988

Filed:

Jun 14, 1985

Appl. No.:

6/744851

Inventors:

Gilbert S. Burrus - Apex NC
Ronald J. Cooper - Raleigh NC
Michael R. Marr - Chapel Hill NC
Mario A. Marsico - Cary NC
John C. Pescatore - Chapel Hill NC
Paul D. Sullivan - Apex NC

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1332

US Classification:

364200

Abstract:

A multi-port communications controller and variable protocol adapter is described. The adapter utilizes a user programmable pluggable programming cartridge for defining individual communications port data service characteristics. The port data service characteristics are interpreted by a microprocessor which manages the interchange from port to port and to or from memory or a host system. Direct memory access or interrupt driven memory access modes of operation are individually selectable for each individual in bound and out bound communications channel. The communications protocols employed at each port may be of any standard type with the microprocessor in the adapter making the appropriate conversion. Communication speeds can be automatically recognized and matched for each port also. An arbitration processor for both DMA and interrupt driven data transfer services is included as the heart of the communications adapter design to provide the capability of individualized control over each in bound and out bound channel's mode of data transfer service for the optimum mode of operation for each port and type of data service required.

US Patent:

55353339, Jul 9, 1996

Filed:

Mar 30, 1993

Appl. No.:

8/040317

Inventors:

James J. Allen - Raleigh NC
Ronald J. Cooper - Raleigh NC
Douglas H. Cox - Raleigh NC
William L. McNeil - Cary NC
Herbert Rivera-Sanchez - Durham NC
Terri L. Tomlinson - Louisburg NC

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

39520003

Abstract:

A system and method for controlling a communications adapter interface such that supplemental data can be interleaved with data being transferred. The interleaving is performed in a manner such that the supplemental data is transparent to the data mover portion of the communications adapter. The supplemental data can be transferred in either read or write cycles that are interleaved at the beginning, in the middle, or at the end of data bursts or block data transfers. As a result of the interleaving, the slave interface bus is more fully utilized because arbitration and bus ownership changes do not create unused cycles. The interleaving is accomplished by temporarily halting an existing transfer of data and transferring the requested supplemental data while the data transfer is halted. After the supplemental data is transferred, the transfer of the balance of the data block is then allowed to continue. In other words, the present invention "steals" a cycle from the data transferror and uses this cycle to transfer supplemental data.

US Patent:

46480293, Mar 3, 1987

Filed:

Aug 27, 1984

Appl. No.:

6/644882

Inventors:

Ronald J. Cooper - Raleigh NC
Mario A. Marsico - Cary NC
John C. Pescatore - Durham NC
Paul D. Sullivan - Apex NC

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 946
G06F 1318
G06F 1324
G06F 1336

US Classification:

364200

Abstract:

In an arbitration apparatus and technique, the request lines from a plurality of potential requestors serve both as interrupt and DMA bus request signal lines to an arbitration device. The arbitration device selects among contending requestors on a priority basis and generates a grant signal interpreted by the requesting devices either as an interrupt grant or a bus grant depending upon whether or not an interrupt acknowledge signal is received. This effectively multiplexes the grant request lines from a plurality of requestors to greatly reduce interconnection complexity and cost. A single interrupt grant/bus grant multi-wire signal cable connects from the arbitration device to the individual requestors. A grant will appear on a single line thereof connected to an individual requestor that has been granted either an interrupt or access to the bus. Interrupt requests from the requestors are ORed together and simultaneously presented to a central controlling microprocessor.

US Patent:

48376779, Jun 6, 1989

Filed:

Jun 14, 1985

Appl. No.:

6/744850

Inventors:

Gilbert S. Burrus - Apex NC
Ronald J. Cooper - Raleigh NC
Michael R. Marr - Chapel Hill NC
Mario A. Marsico - Cary NC
John C. Pescatore - Chapel Hill NC
Paul D. Sullivan - Apex NC

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1332

US Classification:

364200

Abstract:

Bus interconnection between the system busses of a multi-port communications controller and the busses of one or more multi-port adapters is facilitated with a new architecture for providing an interconnection controller. A programmably adjustable adapter and port interface controller is combined via a scannerless communications controller with a bus interconnection control logic that handles both DMA and interrupt mode data transfers for a large number of channels. The invention provides an improved apparatus and method for transferring data to or from numerous communication channel devices within a processor based communications system in such a manner that the optimum mode of data transfer may be individually programmed for each channel as system environment conditions demand.

US Patent:

48705667, Sep 26, 1989

Filed:

Aug 27, 1984

Appl. No.:

6/644889

Inventors:

Ronald J. Cooper - Raleigh NC
Mario A. Marsico - Cary NC
Richard C. Matlack - Raleigh NC
John C. Pescatore - Durham NC
Robert L. Smith - North Easton MA

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

G06F 1300

US Classification:

364200

Abstract:

A communications concentrator and message multiplexer featuring direct access from the communications adapters to main memory via direct memory access means which eliminates the usual scanner or polling facility in a concentrator or multiplexer is described. A control microprocessor manages the allocation of memory, the conversion of message protocols and the servicing of interrupts to a plurality of port interface adapter microprocessors. The interface adapter microprocessors directly set up and control the DMA operation instead of having the DMA operation controlled by the control processor. One of the port adapters serves as a service adapter over a dedicated interface allowing a remote disgnostician access to internal registers in the control processor system, access to a dedicated read only storage for servicing, and logical interface to the main control processor for the purpose of entering instructions and directing functional operations to test each component of the system.