Ronald J Lange

US Patent:

6457091, Sep 24, 2002

Filed:

May 14, 1999

Appl. No.:

09/311911

Inventors:

Ronald E. Lange - Glendale AZ
David Ross Evoy - Tempe AZ

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

G06F 1336

US Classification:

710314, 710303

Abstract:

A computer system includes a host processor, a first PCI bus, a second PCI bus and a PCI-to-PCI bridge. The first PCI bus is coupled with the host processor. The PCI-to-PCI bridge interconnects the first and second PCI buses. The PCI-to-PCI bridge includes a first portion and a second portion. The first portion includes a first configuration register and the second portion includes a second configuration register. A method is also taught.

US Patent:

6581125, Jun 17, 2003

Filed:

May 14, 1999

Appl. No.:

09/312206

Inventors:

Ronald E. Lange - Glendale AZ
David Ross Evoy - Tempe AZ

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

G06F 1314

US Classification:

710305, 710300, 710310

Abstract:

A computer system includes a host processor, a first PCI bus, a second PCI bus and a bus bridge. The first PCI bus is coupled with the host processor. The bus bridge interconnects the first and second PCI buses. The bus bridge includes a first portion having a first bridge memory, a second portion having a second bridge memory, and a latency inducing serial bus interconnecting the first portion and the second portion. A method is also taught.

US Patent:

39797260, Sep 7, 1976

Filed:

Apr 10, 1974

Appl. No.:

5/459504

Inventors:

Ronald Edwin Lange - Phoenix AZ
Riley H. Dobberstein - Scottsdale AZ
Steven Hugh Webber - Groton MA

Assignee:

Honeywell Information Systems, Inc. - Phoenix AZ

International Classification:

G06F 1300

US Classification:

3401725

Abstract:

In a data processing system that uses segmentation and paging to access data information such as in a virtual memory machine, the cache store need not be entirely cleared each time an I/O operation is performed or each time the data in the cache has a possibility of being incorrect. With segmentation and paging, only a portion of the cache store need be cleared when a new page is obtained from the virtual memory. The entire cache store is cleared only when a new segment is indicated by the instruction. The cache store is selectively cleared of the information from the page whose data information is no longer needed by addressing each level of an associative tag directory to the cache store. The columns of each level are compared to the page address and if a comparison is signaled that column of the addressed level is cleared by clearing the flag indicating the full status of the column in the addressed level. Each level of the tag directory is addressed.

US Patent:

53676998, Nov 22, 1994

Filed:

Nov 26, 1991

Appl. No.:

7/800343

Inventors:

Ronald E. Lange - Glendale AZ
Russell W. Guenthner - Glendale AZ
Leonard Rabins - Scottsdale AZ

Assignee:

Bull HN Information Systems Inc. - Technology Park MA

International Classification:

G06F 762

US Classification:

395800

Abstract:

In order to obtain precise submodel control in a central processing unit, there is provided a subcounter which is controlled to count up from a beginning count as an instruction is executed and to count back down at the same rate to the reference count to obtain an effective delay before processing of the next instruction to be processed during normal program execution is started. Instruction transfer and decoding of the new instruction entering the pipeline is inhibited until the subcounter's most significant bit ("sign bit") changes state. If the subcounter is allowed to count during the entire count up and count down periods, a derated mode of 1/2 is achieved. To obtain other fractions, the subcounter is controlled to count periodically during one count direction period and to count full time during the other count direction period. In the exemplary embodiment, 1/4 and 3/4 derating is selectively achieved by the use of a modulo 3 counter which allows the subcounter to count only 1/3 the time in one or the other of the subcounter count up or count down periods.

US Patent:

48316229, May 16, 1989

Filed:

Dec 22, 1987

Appl. No.:

7/136301

Inventors:

Marion G. Porter - Phoenix AZ
Marvin K. Webster - Glendale AZ
Ronald E. Lange - Glendale AZ

Assignee:

Honeywell Bull Inc. - Phoenix AZ

International Classification:

G06F 1110

US Classification:

371 10

Abstract:

In a data processing system, there is included a central processing unit (CPU) and a main memory for storing computer words, the CPU including a cache unit. In operation, the CPU requests that a computer word be fetched, the computer word to be fetched being identified by a real address location corresponding to a location where the predetermined computer word is stored in main memory. The CPU request to fetch the computer word is coupled through the cache unit such that the cache unit determines whether the computer word is stored within the cache unit. The cache unit comprises a cache for storing predetermined ones of the compter words. A directory is included for storing partial real address information to a corresponding computer word stored in the cache. A detecting element, operatively connected to the cache and to the directory, determines when a hit occurs without any errors. Control logic, operatively connected to the detecting element, makes available to the CPU the requested computer word from the cache or the main memory when an error is detected as a result of attempting to obtain the computer word from the cache.

US Patent:

55070000, Apr 9, 1996

Filed:

Sep 26, 1994

Appl. No.:

8/311797

Inventors:

Wilbur L. Stewart - Phoenix AZ
Ronald E. Lange - Glendale AZ
Richard L. Demers - Peoria AZ
Jeffrey D. Weintraub - Scottsdale AZ

Assignee:

Bull HN Information Systems Inc. - Billerica MA

International Classification:

G06F 900
G06F 9302

US Classification:

395800

Abstract:

In a central processor incorporating at least one co-processor, such as a floating point arithmetic co-processor, in addition to a basic arithmetic logic unit, the problem of rationalizing the contents of the accumulator and supplementary accumulator registers without the burden of speed penalties is addressed and solved. This is achieved by providing input/output access to a common register file and by switching control of the register file to the proper processing unit appropriately. A single, shared accumulator register and a single, shared supplementary accumulator register are included in the stack along with other sharable registers such as address modification registers. Thus, the contents of the accumulator register and the supplementary accumulator register are always up-to-date and available to all processing units in the central processor without the need for first carrying out rationalization steps.

US Patent:

55155294, May 7, 1996

Filed:

Mar 25, 1994

Appl. No.:

8/218538

Inventors:

William A. Shelly - Phoenix AZ
Ronald E. Lange - Glendale AZ
Donald C. Boothroyd - Phoenix AZ

International Classification:

G06F 1540

US Classification:

395180

Abstract:

In order to validate data manipulation results in a CPU which incorporates duplicate BPUs for integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation operations, a first BPU transfers to cache storage only the even bits of a given data manipulation result, and a second BPU correspondingly transfers to cache storage only the odd bit information of the result. One BPU segregates the even bits of the result, adds parity information and sends the even bits and parity information to the cache unit. Similarly, the second BPU segregates the odd bits of the result, adds parity information and sends the odd bits and parity information to the cache unit. In the cache unit, the even and odd bit information are separately parity checked before storage into cache memory. If a parity error is observed in either set of information, an error signal is issued to institute appropriate remedial action.

US Patent:

43342892, Jun 8, 1982

Filed:

Feb 25, 1980

Appl. No.:

6/124008

Inventors:

Ronald E. Lange - Phoenix AZ
Richard J. Fisher - Phoenix AZ

Assignee:

Honeywell Information Systems Inc. - Phoenix AZ

International Classification:

G06F 700

US Classification:

364900

Abstract:

There is disclosed herein an apparatus for encoding, storing, updating and decoding data indicating the order of usage of memory locations as in a cache memory. An array of memory bits is encoded by a field programmable logic array each time a memory device or other peripheral is accessed by a method which need change only a portion of all the memory bits in a row. Each row corresponds to a group of memory locations or peripherals to be monitored. When the order of usage of a group of monitored locations is to be determined a field programmable logic array decodes the corresponding row and outputs a signal indicating the least recently used one of the memory locations of interest.