Ronald S Larson

US Patent:

47198400, Jan 19, 1988

Filed:

Jun 7, 1985

Appl. No.:

6/742244

Inventors:

Bradley D. Goodell - Anoka MN
Ronald A. Larson - Minneapolis MN

Assignee:

FMC Corporation - Chicago IL

International Classification:

F41F 906

US Classification:

89 47

Abstract:

A compact rammer assembly for forcing ammunition into a gun having a rammer head attached to a pair of chains which are stored in separate spiral tracks positioned between the retracted position of the rammer head and driven sprockets. Each chain composed of links pinned together with vertical tabs at each end of each link; the tabs on each link engaging the tabs on adjacent links of each chain as well as the corresponding tabs on the links of the other chain when the sprockets driven the chains to extend the rammer head.

US Patent:

50974378, Mar 17, 1992

Filed:

Jul 17, 1988

Appl. No.:

7/217542

Inventors:

Ronald J. Larson - Minneapolis MN

International Classification:

G06F 900
G06F 1310

US Classification:

395775

Abstract:

A controller for controlling a microprocessor-based system incorporates two cooperatively operating state machine controllers and is capable of interfacing with bus and memory subsystems while maintaining synchronous handshake with more than one type of microprocessor on a bus which may operate at a different speed than the system memory subsystems and peripheral devices. The controller provides functional and timing parameters to satisfy requirements for an asynchronous bus and for more than one type of device which reside on the bus.

US Patent:

52206513, Jun 15, 1993

Filed:

Oct 11, 1989

Appl. No.:

7/419096

Inventors:

Ronald J. Larson - Minneapolis MN

Assignee:

Micral, Inc. - New Brighton MN

International Classification:

G06F 1300
G06F 1338

US Classification:

395250

Abstract:

A synchronous bus controller which provides a functional control link between one or more microprocessors and an asychronous main input/output bus is provided. The bus controller includes a state machine and data bus width determining logic enabling the bus controller to initiate and control access operations between microprocessors and accessible devices on the main input/output bus when the microprocessor and the accessed device may have different data bus widths. The bus controller includes logic circuitry to determine the number of access cycles required to complete a requested access operation and detects the last access cycle of a current access operation to terminate an access operation and provide a ready signal to the microprocessor indicating that the bus controller is ready for the next access request.

US Patent:

52206599, Jun 15, 1993

Filed:

Sep 18, 1989

Appl. No.:

7/409435

Inventors:

Ronald J. Larson - Minneapolis MN
Jeffry V. Herring - Bloomington MN

Assignee:

Micral, Inc. - New Brighton MN

International Classification:

G06F 1314
G06F 1320
G06F 13372

US Classification:

395500

Abstract:

A controller for interfacing bus-coupled peripheral devices with a microcomputer is described. The controller provides generalized compensation for variations in peripheral device access recovery time and for differences in access recovery times among peripheral devices, central processing units and input/output buses.

US Patent:

54127955, May 2, 1995

Filed:

Feb 25, 1992

Appl. No.:

7/840883

Inventors:

Ronald J. Larson - Minneapolis MN

Assignee:

Micral, Inc. - New Brighton MN

International Classification:

G06F 1500

US Classification:

395500

Abstract:

A finite state machine has outputs variable between a finite number of logical outputs states. A clock provides a clock signal having clock pulses, with a frequency, to the state machine. A functional circuit determines the logical output states of the state machine based on state inputs to the functional circuit. A variable timer is coupled to the clock and the functional circuit. The variable timer controls the duration of each logical output state to adjust for changes in the clock frequency based on timing parameters provided to the variable timer. The variable timer varies a number of clock pulses corresponding to each logical output state so the duration of each logical output state remains within a predetermined time limit.

US Patent:

52690067, Dec 7, 1993

Filed:

Apr 8, 1992

Appl. No.:

7/866948

Inventors:

William F. Dohse - Plymouth MN
Ronald J. Larson - Minneapolis MN
Richard Mansfield - Bloomington MN

Assignee:

Micral, Inc. - New Brighton MN

International Classification:

G06F 1332

US Classification:

395325

Abstract:

A microprocessor access arbitration network which arbitrates among HOLD, RESET and REFRESH request commands by controlling a preempt bus so that a system memory refresh cycle is never delayed by a DMA or bus master operation is described. If a HOLD request is in progress for an operation other than a REFRESH cycle when a REFRESH cycle is initiated, that HOLD request is delayed while the REFRESH cycle proceeds to completion.

US Patent:

51877791, Feb 16, 1993

Filed:

Aug 11, 1989

Appl. No.:

7/392705

Inventors:

Joseph M. Jeddeloh - Minneapolis MN
Ronald J. Larson - Minneapolis MN
Jeffry V. Herring - Bloomington MN

Assignee:

Micral, Inc. - New Brighton MN

International Classification:

G06F 1300
G06F 1314

US Classification:

395325

Abstract:

An asynchronous memory control Unit for asynchronously controlling access to and from system memory of a microcomputer system in response to control signals from conventional and state-of-the-art microcomputer I/O buses is described. The asynchronous memory control unit of the present invention operates cooperatively with a synchronous memory control unit which provides access to and from system memory in response to command signals from a microprocessor. Whenever the microprocessor controls the bus, the synchronous memory control unit is enabled; whenever the microprocessor is not controlled of the bus at main IO bus, the asynchronous control unit is enabled.

US Patent:

54559308, Oct 3, 1995

Filed:

Sep 9, 1992

Appl. No.:

7/942753

Inventors:

Ronald J. Larson - Minneapolis MN

Assignee:

Micral, Inc. - New Brighton MN

International Classification:

G06F 1342
G06F 1338
G06F 1300

US Classification:

395550

Abstract:

A state machine in a computer system receives operation parameters, a clock signal and control signals from a control device. The state machine provides output signals in logical output states to perform an operation based on the operation parameters, the clock signal and the control signals. The operation parameters provided by the control device include timing parameters and state parameters which are stored. A counter provides a counter output based on the clock signal and based on the stored timing parameters. A counter control circuit compares the counter output with timing parameters and controls operation of the counter based on the control signals provided by the control device and based on the comparison of the counter output with the timing parameters. A state generator compares the counter output with the state parameters and generates the output signals in logical output states, each logical output state having a duration based on the comparison of the counter output with the state parameters.