Ronald J Larson

US Patent:

47198400, Jan 19, 1988

Filed:

Jun 7, 1985

Appl. No.:

6/742244

Inventors:

Bradley D. Goodell - Anoka MN
Ronald A. Larson - Minneapolis MN

Assignee:

FMC Corporation - Chicago IL

International Classification:

F41F 906

US Classification:

89 47

Abstract:

A compact rammer assembly for forcing ammunition into a gun having a rammer head attached to a pair of chains which are stored in separate spiral tracks positioned between the retracted position of the rammer head and driven sprockets. Each chain composed of links pinned together with vertical tabs at each end of each link; the tabs on each link engaging the tabs on adjacent links of each chain as well as the corresponding tabs on the links of the other chain when the sprockets driven the chains to extend the rammer head.

US Patent:

56405855, Jun 17, 1997

Filed:

Jun 6, 1995

Appl. No.:

8/468030

Inventors:

Charles H. Smoot - Orono MN
Ronald J. Larson - Minneapolis MN
Jeffry V. Herring - Bloomington MN
Jean-Pierre Dupont - Chilly-Mazarin, FR
Richard Matysiak - Orsay, FR

Assignee:

AST Research, Inc. - Irvine CA

International Classification:

G06F 100

US Classification:

395800

Abstract:

A state machine bus controller for interfacing the CPU of a micro-computer based system with memory and I/O device is described. The controller, while capable of interfacing with a bus which is synchronous in nature, can maintain synchronous handshake with more than one type of microprocessor while providing function and timing parameters to satisfy requirements of an asynchronous bus and more than one type of device which reside on the bus.

US Patent:

59447990, Aug 31, 1999

Filed:

Jun 16, 1997

Appl. No.:

8/876926

Inventors:

Charles H. Smoot - Orono MN
Ronald J. Larson - Minneapolis MN
Jeffry V. Herring - Bloomington MN
Jean-Pierre Dupont - Chilly-Mazarin, FR
Richard Matysiak - Orsay, FR

Assignee:

Samsung Electronics Co., Ltd. - Suwon

International Classification:

G06F 1314

US Classification:

710 8

Abstract:

A state machine bus controller for interfacing the CPU of a micro-computer based system with memory and I/O device is described. The controller, while capable of interfacing with a bus which is synchronous in nature, can maintain synchronous handshake with more than one type of microprocessor while providing function and timing parameters to satisfy requirements of an asynchronous bus and more than one type of device which reside on the bus.