Ronald Jay Mack

US Patent:

6367041, Apr 2, 2002

Filed:

Sep 26, 2000

Appl. No.:

09/670992

Inventors:

Mihai G. Statovici - San Jose CA
Ronald J. Mack - Gilroy CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G01R 3128

US Classification:

714724, 324 731

Abstract:

A method and software apparatus for implementing a dynamically modifiable test flow for integrated circuit devices that adapts to the characteristics of each processed device lot. A modified set of tests sufficient to ensure proper device function for a particular lot is performed, reducing test costs and increasing test capacity. The method and system of the invention periodically samples a predetermined sample number of devices using a full set of tests including a set of skippable tests. Depending upon the performance characteristics of the sample device group on the skippable tests, a number of skippable tests are skipped during a modified test flow. After a next set of devices is tested using the modified test flow, the full set of tests is again performed on another sample group, and the size and makeup of the modified test flow is adjusted according to the new results.

US Patent:

6552526, Apr 22, 2003

Filed:

May 23, 2000

Appl. No.:

09/578793

Inventors:

Mihai G. Statovici - San Jose CA
Ronald J. Mack - Gilroy CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G01R 1900

US Classification:

3241581, 324 7611

Abstract:

A method and system are provided for increasing the accuracy of AC parametric testing. The invention provides a method of precisely estimating signal propagation delay time in an integrated circuit testing apparatus, wherein a plurality of signal propagation delay time measurements are taken and additional delay times are estimated by linearly interpolating the measured delays. A desired test point (desired output voltage at a given time) is established. Using a sample device, a slope is established on a time vs. voltage plot for a line through the desired test point. Where a desired test point falls between strobe times on a tester, linear extrapolation is used to calculate what voltages must be tested for at the two bracketing strobe times in order to guarantee the desired performance at the desired test point. One or more devices are then tested for the calculated voltages at the corresponding bracketing strobe times.

US Patent:

59236027, Jul 13, 1999

Filed:

Mar 19, 1998

Appl. No.:

9/044584

Inventors:

Mihai G. Statovici - San Jose CA
Ronald J. Mack - Gilroy CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G11C 700

US Classification:

365201

Abstract:

A method is described for testing the programming function of integrated circuit device cells including floating gate elements. To accelerate the testing process, at most two programming pulses are needed, the two pulses being applied with the device at minimum and maximum power supply voltage levels specified for the device. First, the cell state after an initial programming pulse with the device at a minimum power supply voltage level, tested against a minimum reference voltage level, indicates whether the cell is programming properly. If not, testing ceases immediately and the device is rejected after the first pulse. Devices passing the first reading after the first pulse are subjected to a second reading at the target (higher) reference voltage. Devices passing after the second reading are designated as passing and are subjected to the next test in the test flow. Devices failing the second reading are subjected to a second programming pulse, applied with the device at the maximum power supply voltage level, the resulting cell state providing an indication of cell programming functionality.

US Patent:

53607473, Nov 1, 1994

Filed:

Jun 10, 1993

Appl. No.:

8/074897

Inventors:

Sheldon O. Larson - San Jose CA
Ronald J. Mack - Gilroy CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H01L 2166
G01R 3126

US Classification:

437 8

Abstract:

A method is provided which includes on-chip identification of individual die. The first wafer sort includes the steps of programming a plurality of dice on a wafer, programming predetermined memory memory cells on each good die to identify the wafer on which that die is located, and storing the location of each good die in a file created for each wafer. Then, the plurality of dice are subjected to predetermined conditions. In the second wafer sort, predetermined memory cells on one die are accessed to determine the associated file of that die. The associated file is then loaded. Finally, the good dice are tested. In another embodiment, the first wafer sort includes identifying the first good die on the wafer. After the next good die on the wafer is found, that die is programmed to indicate the location of the proceeding good die. This programming step is repeated until the last good die on the wafer is programmed.

US Patent:

61752460, Jan 16, 2001

Filed:

May 23, 2000

Appl. No.:

9/577193

Inventors:

Mihai G. Statovici - San Jose CA
Ronald J. Mack - Gilroy CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G01R 3126

US Classification:

324765

Abstract:

A method and system are provided for increasing the accuracy of AC parametric testing. The invention provides a method of precisely estimating signal propagation delay time in an integrated circuit testing apparatus, wherein a plurality of signal propagation delay time measurements are taken and additional delay times are estimated by linearly interpolating the measured delays. A desired test point (desired output voltage at a given time) is established. Using a sample device, a slope is established on a time vs. voltage plot for a line through the desired test point. Where a desired test point falls between strobe times on a tester, linear extrapolation is used to calculate what voltages must be tested for at the two bracketing strobe times in order to guarantee the desired performance at the desired test point. One or more devices are then tested for the calculated voltages at the corresponding bracketing strobe times.

US Patent:

61247243, Sep 26, 2000

Filed:

May 27, 1998

Appl. No.:

9/085983

Inventors:

Mihai G. Statovici - San Jose CA
Ronald J. Mack - Gilroy CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G01R 3126

US Classification:

324765

Abstract:

A method and system are provided for increasing the accuracy of AC parametric testing. The invention provides a method of precisely estimating signal propagation delay time in an integrated circuit testing apparatus, wherein a plurality of signal propagation delay time measurements are taken and additional delay times are estimated by linearly interpolating the measured delays. A desired test point (desired output voltage at a given time) is established. Using a sample device, a slope is established on a time vs. voltage plot for a line through the desired test point. Where a desired test point falls between strobe times on a tester, linear extrapolation is used to calculate what voltages must be tested for at the two bracketing strobe times in order to guarantee the desired performance at the desired test point. One or more devices are then tested for the calculated voltages at the corresponding bracketing strobe times.

US Patent:

61675458, Dec 26, 2000

Filed:

Mar 19, 1998

Appl. No.:

9/044585

Inventors:

Mihai G. Statovici - San Jose CA
Ronald J. Mack - Gilroy CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G01R 3128

US Classification:

714724

Abstract:

A method and software apparatus are provided for implementing a dynamically modifiable test flow for integrated circuit devices that adapts to the characteristics of each processed device lot. According to the method of the invention, a modified set of tests sufficient to ensure proper device function for a particular lot is performed, reducing test costs and increasing test capacity. The method and system of the invention periodically samples a predetermined sample number of devices using a full set of tests including a set of skippable tests. Depending upon the performance characteristics of the sample device group on the skippable tests, a number of skippable tests are skipped during a modified test flow. After a next set of devices is tested using the modified test flow, the full set of tests is again performed on another sample group, and the size and makeup of the modified test flow is adjusted according to the new results. A test summary logs the results of regular and skippable tests, providing user access to enable system modification according to desired acceptance quality levels.