Ronald Antione Rose

US Patent:

6567773, May 20, 2003

Filed:

Nov 17, 1999

Appl. No.:

09/441797

Inventors:

Khalid Rahmat - Yorktown NY
Ronald D. Rose - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1750

US Classification:

703 14, 326 27, 326 83

Abstract:

A method and structure for analyzing the effect of electrical noise in an integrated circuit fabricated in a silicon-on-insulator (âSOIâ) technology. The present invention uses a static noise analysis to evaluate an integrated circuits response to electrical noise, taking into account hysteresis effect and parasitic bipolar current voltage, both of which are unique to integrated circuits fabricated in a SOI technology process. The present invention also includes a computer, computer storage device, computer program and software incorporating the method steps and simulating the testing and analysis of the circuit under test.

US Patent:

7089513, Aug 8, 2006

Filed:

Mar 19, 2004

Appl. No.:

10/708715

Inventors:

Karen A. Bard - Hopewell Junction NY, US
Ronald D. Rose - Essex Junction VT, US
Michael H. Sitko - Jericho VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 4, 716 5, 716 1

Abstract:

A method, system and program product for designing an integrated circuit (IC) for signal integrity. The invention conducts a signal integrity analysis on an IC design; identifies any field effect transistor (FET) that causes a signal integrity failure in the case that the IC design fails the signal integrity analysis; and modifies an edge of a failing FET that is closer than a threshold distance to a well edge. The invention eliminates the manual, iterative procedure for determining the device causing a signal integrity failure due to well proximity effects.

US Patent:

20030188267, Oct 2, 2003

Filed:

Mar 29, 2002

Appl. No.:

10/063214

Inventors:

Timothy Lehner - Hopewell Junction NY, US
Khalid Rahmat - Yorktown Heights NY, US
Ronald Rose - Essex Junction VT, US
Rouwaida Kanj - Champaign IL, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F017/50

US Classification:

716/001000

Abstract:

A circuit model and method for modeling circuit waveforms. The elements present in the basic model are capacitors and ideal current sources. The adaptability and accuracy of the model is made possible by explicitly tabulating all element values as simultaneous functions of all input and output voltages, and using a high-dimensional interpolation technique of arbitrary order. The topology chosen is the simplest one that still shows the necessary qualitative features and allows for simple generalization to multiple input/output pins. Accuracy is also provided by the implicit nature of the ordinary differential equation (ODE) used to solve for the output voltages.

US Patent:

20190347379, Nov 14, 2019

Filed:

Jul 22, 2019

Appl. No.:

16/517990

Inventors:

- Armonk NY, US
Mark A. Lavin - Katonah NY, US
Ronald D. Rose - Essex Junction VT, US
Richard W. Taggart - Poughkeepsie NY, US
Vladimir Zolotov - Putnam Valley NY, US

International Classification:

G06F 17/50

Abstract:

A computer-implemented method includes identifying a noise cluster, representing the noise cluster according to a variational model, projecting the variational model onto one or more corners to yield a projected noise cluster, and determining a computed noise for the projected noise cluster. Optionally, the noise cluster includes one or more noise cluster elements, and each of the noise cluster elements are expressed as one or more circuit element terms, according to a canonical form. Optionally, at least one of the corners is a bounding corner. For the bounding corner, the projected noise cluster is generated by maximizing the circuit element terms for those noise cluster elements that tend to increase noise, and by minimizing the circuit element terms for those noise cluster elements that tend to decrease noise, whereby noise is maximized for the canonical form. A corresponding computer program product and computer system are also disclosed.

US Patent:

20180082009, Mar 22, 2018

Filed:

Dec 5, 2017

Appl. No.:

15/832249

Inventors:

- Armonk NY, US
Susan E. Cellier - Hopewell Junction NY, US
Anthony D. Hagin - Poughkeepsie NY, US
Adam P. Matheny - Beacon NY, US
Ronald D. Rose - Essex Junction VT, US
David J. Widiger - Pflugerville VT, US

International Classification:

G06F 17/50

Abstract:

Disclosed is a method for improving capacitance extraction performance in a circuit, the method including mapping, via a computing resource, a first layout including a plurality of wiring paths, selecting at least one target wire from the plurality of wiring paths, selecting at least one group of wires running orthogonally to the at least one target wire, identifying and selecting within the at least one group at least one set of two or more wires that are combinable for representation as a single merged wire, mapping a second layout, via the computing resource, and representing the at least one set of two or more wires as the single merged wire in said second layout, analyzing parasitic capacitance between the at least one target wire and the at least one group of wires using the second layout, and manufacturing the circuit using information from the analyzing of parasitic capacitance.

US Patent:

20170161422, Jun 8, 2017

Filed:

Dec 8, 2015

Appl. No.:

14/962185

Inventors:

- Armonk NY, US
Susan E. Cellier - Hopewell Junction NY, US
Anthony D. Hagin - Poughkeepsie NY, US
Adam P. Matheny - Beacon NY, US
Ronald D. Rose - Essex Junction VT, US
David J. Widiger - Pflugerville TX, US

International Classification:

G06F 17/50

Abstract:

Disclosed is a method for improving capacitance extraction performance in a circuit, the method including mapping, via a computing resource, a first layout including a plurality of wiring paths, selecting at least one target wire from the plurality of wiring paths, selecting at least one group of wires running orthogonally to the at least one target wire, identifying and selecting within the at least one group at least one set of two or more wires that are combinable for representation as a single merged wire, mapping a second layout, via the computing resource, and representing the at least one set of two or more wires as the single merged wire in said second layout, analyzing parasitic capacitance between the at least one target wire and the at least one group of wires using the second layout, and manufacturing the circuit using information from the analyzing of parasitic capacitance.

US Patent:

20170140090, May 18, 2017

Filed:

Nov 18, 2015

Appl. No.:

14/944552

Inventors:

- Armonk NY, US
Mark A. Lavin - Katonah NY, US
Ronald D. Rose - Essex Junction VT, US
Richard W. Taggart - Poughkeepsie NY, US
Vladimir Zolotov - Putnam Valley NY, US

International Classification:

G06F 17/50

Abstract:

A computer-implemented method includes identifying a noise cluster, representing the noise cluster according to a variational model, projecting the variational model onto one or more corners to yield a projected noise cluster, and determining a computed noise for the projected noise cluster. Optionally, the noise cluster includes one or more noise cluster elements, and each of the noise cluster elements are expressed as one or more circuit element terms, according to a canonical form. Optionally, at least one of the corners is a bounding corner. For the bounding corner, the projected noise cluster is generated by maximizing the circuit element terms for those noise cluster elements that tend to increase noise, and by minimizing the circuit element terms for those noise cluster elements that tend to decrease noise, whereby noise is maximized for the canonical form. A corresponding computer program product and computer system are also disclosed.