Rotem Oshman

US Patent:

20120159504, Jun 21, 2012

Filed:

Dec 17, 2010

Appl. No.:

12/971983

Inventors:

Rotem Oshman - Cambridge MA, US
John R. Douceur - Bellevue WA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 9/46

US Classification:

718104

Abstract:

Techniques for implementing mutual-exclusion algorithms that are also fault-resistant are described herein. For instance, this document describes systems that implement fault-resistant, mutual-exclusion algorithms that at least prevent simultaneous access of a shared resource by multiple threads when (i) one of the multiple threads is in its critical section, and (ii) the other thread(s) are waiting in a loop to enter their respective critical sections. In some instances, these algorithms are fault-tolerant to prevent simultaneous access of the shared resource regardless of a state of the multiple threads executing on the system. In some instances, these algorithms may resist (e.g., tolerate entirely) transient memory faults (or “soft errors”).