Rui Niu

US Patent:

20130186676, Jul 25, 2013

Filed:

Jan 20, 2012

Appl. No.:

13/355128

Inventors:

Fei Yu - Santa Clara CA, US
Anwar A. Mohammed - San Jose CA, US
Rui Niu - Sunnyvale CA, US

Assignee:

FutureWei Technologies, Inc. - Plano TX

International Classification:

H05K 1/09
H05K 1/00
H05K 1/16
H05K 3/46
H05K 3/00

US Classification:

174257, 427 972, 29829, 174260, 174258

Abstract:

A structure for a core layer of a substrate and a method for fabricating a core layer of a substrate are disclosed. The core layer comprises a molding compound encapsulating a die or a plurality of dies, a dielectric layer on the surfaces of the molding compound, and a conductive layer on top of the dielectric layer. A through hole is formed through the dielectric layer and the molding compound, which may be filled with a metal plate. A laser via is formed similarly. Build-up layers may be assembled next to the core layer to form the substrate, which can be used to package dies.

US Patent:

20140070406, Mar 13, 2014

Filed:

May 17, 2013

Appl. No.:

13/897156

Inventors:

Weifeng Liu - Dublin CA, US
Rui Niu - Cupertino CA, US

International Classification:

H01L 23/498
H01L 23/48

US Classification:

257737, 257773

Abstract:

Polyimide-based redistribution layers (RDLs) can be employed to reduce thermo-mechanical stress that is exerted on conductive interconnections bonded to interposers in 2.5 D semiconductor packaging configurations. The polyimide-based RDL is located on an upper or lower face of an interposer. Additionally, height differentials between laterally adjacent semiconductor dies in 2.5 D semiconductor packages can be reduced or eliminated by using different diameter micro-bumps, different height copper pillars, or a multi-tiered interposer to lower taller semiconductor dies in relation to shorter semiconductor dies.

US Patent:

8519543, Aug 27, 2013

Filed:

Jul 17, 2012

Appl. No.:

13/551466

Inventors:

Haoyu Song - Cupertino CA, US
Cao Wei - Cupertino CA, US
Rui Niu - Cupertino CA, US
Anwar A. Mohammed - San Jose CA, US

Assignee:

Futurewei Technologies, Inc. - Plano TX

International Classification:

H01L 23/48

US Classification:

257774, 257700

Abstract:

A multi-die integrated circuit assembly includes an interposer substrate larger than the typical reticle size used in fabricating the “active area” in which the through-silicon vias (TSVs) and interconnect conductors are formed in the interposer. At the same time, each of the dies has its external power/ground and I/O signal line connections concentrated into a smaller area of the die. The dies are disposed or mounted on the interposer such that these smaller areas (with the power/ground/IO connections) overlap with the active area of the interposer. In this configuration, a plurality of dies having a combined area substantially greater than the active area of the interposer can be mounted on the interposer (and take advantage of the active area for interconnections).