Russell Anderson

US Patent:

46169652, Oct 14, 1986

Filed:

Feb 27, 1984

Appl. No.:

6/583712

Inventors:

Russell W. Anderson - Milwaukie OR
Michael J. Held - Portland OR

Assignee:

Manufacturers Tool Service, Inc. - Portland OR

International Classification:

B23B 2710

US Classification:

408204

Abstract:

An indexable shell cutter having an improved cartridge for mounting a cutter insert on the cutting face of the shell cutter body. The cutter body has a plurality of recesses extending rearwardly from the cutting face, each of said recesses being formed by a first surface, a second surface spaced from the first surface, and a base surface extending between the first and second surfaces. The second surface is essentially perpendicular to the plane of the cutting face of the cutter head and is V-shaped in cross-section. A cartridge is removably secured in each of the recesses with the base of the cartridge being in mating engagement with the second surface of the recess. A replaceable and indexable cutter insert having a plurality of cutting edges is releasably secured in a recessed seat located in the outer end of each cartridge with the plane of its face being perpendicular to the plane of the cutting face of the cutter head and one of its cutting edges extending beyond the periphery of a cutting head a distance sufficient to cuttingly engage a workpiece. The other cutting edges of the cutter insert are matingly engaged with the walls of a recessed seat formed in the outer face of the cartridge.

US Patent:

45609810, Dec 24, 1985

Filed:

Mar 23, 1983

Appl. No.:

6/478180

Inventors:

Ronald M. Jackson - Portland OR
Daniel C. Olin - Portland OR
Russell Y. Anderson - Hillsboro OR

Assignee:

Tektronix, Inc. - Beaverton OR

International Classification:

G06F 314

US Classification:

340747

Abstract:

Disclosed herein is an apparatus for displaying a logic waveform on a raster scan display device such as a CRT. A part of an input logic signal is delayed for forming a former bit, and the input logic signal acts as a present bit. A memory device stores a special pattern determined in accordance with results of logic operation of the present and former bits. An image dot of the pattern is addressed by the present and former bits and raster line position (number) information, and the output therefrom is applied as an intensity control signal to the display device. Since the memory device does not need FONT information, this invention needs very little software manipulation of data, and the capacity of the memory device is small. In addition, this invention can display glitches and graticule tick marks.

US Patent:

45786666, Mar 25, 1986

Filed:

Mar 23, 1983

Appl. No.:

6/478115

Inventors:

Russell Y. Anderson - Hillsboro OR

Assignee:

Tektronix, Inc. - Beaverton OR

International Classification:

G06F 702
G05B 100

US Classification:

3401462

Abstract:

A method of comparing first and second data acquired asynchronously allows an effective comparison therebetween even if aliasing errors have occurred during acquisition thereof. Bits of the first and second data are compared in groups of three to obtain relationships therebetween. These relationships indicate if first data is equal to the second data, or the first data can be shifted right and/or left to achieve the second data. This comparison is repeated on successive groups of bits, but the comparison bits used in each data are shifted by a bit for each comparison. If any relationship indicates that the first data was shifted right (or left), then all other comparisons must indicate that the first data matches or is shifted right (or left), for the first data to be found the same as the second data. The presence of both right and left shift relationships indicates that the first and second data cannot be the same.

US Patent:

46138560, Sep 23, 1986

Filed:

Apr 4, 1983

Appl. No.:

6/481557

Inventors:

Daniel C. Olin - Portland OR
Russell Y. Anderson - Hillsboro OR
Steven C. DenBeste - Beaverton OR

Assignee:

Tektronix, Inc. - Beaverton OR

International Classification:

G09G 100

US Classification:

340723

Abstract:

An electrical circuit is described that requires a reduced number of data bits for character-address and video-mode information by using a predetermined bit combination of the video-mode information as part of the character-address information. Character-address and video-mode information is output from a random access memory (RAM) to a character read only memory (ROM) and a video-mode detection circuit that produces outputs to enable video-mode circuits in the video control circuitry. One output of the video-mode detection circuit is coupled to an address input of the character ROM that has characters divided into two character sets. A predetermined bit combination of the video-mode information produces an output from the video-mode detection circuit that selects one of the character sets while the other bit combinations produce an output from the detection circuit that selects the other character set. In this way, character-address and video-mode information having n data bits can produce character and video-mode outputs that normally require n+1 data bits.

US Patent:

45660824, Jan 21, 1986

Filed:

Mar 23, 1983

Appl. No.:

6/478181

Inventors:

Russell Y. Anderson - Hillsboro OR

Assignee:

Tektronix, Inc. - Beaverton OR

International Classification:

G11C 800

US Classification:

365230

Abstract:

Disclosed herein is a system for addressing a memory pack having a plurality of memory chips such as RAMs or ROMs. Each memory chip receives address signals and a chip enable signal. A chip selector generates the chip enable signal in response to a feedback signal from the memory pack provided in response to the memory address lines. Since each memory pack excludes the chip selector circuitry, the memory packs can be made smaller in size. The memory packs are in effect self-configuring since they control the feedback of the address signals to the chip selector which generates the chip enable signals. Many types and capacities of memory packs can be mixed in the system since the pack determines the memory address space in which it resides.