Russell D Cook

US Patent:

52531953, Oct 12, 1993

Filed:

Feb 4, 1993

Appl. No.:

8/013541

Inventors:

Harold J. Broker - Ulster Park NY
Russell S. Cook - Poughkeepsie NY
James O'Connor - Ulster Park NY
Nelson S. Xu - Hyde Park NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 752
G06F 1100

US Classification:

364759

Abstract:

A high speed digital multiplier utilizes a variation in known shift-and-add algorithms. Each cycle, a single digit of the multiplier and the entire multiplicand are processed to form a "partial product" that is added to the result of the next cycle. The end result is a two part product, the high order product being generated by a carry-propagate adder, and the low order product being generated by a "spill adder" that produces one digit each cycle. Inputs of a carry-propagate adder are fed directly from outputs of a carry-save adder rather than running sum and carry registers. With a multiplier digit of 16-bits, a fixed point halfword multiply requires one execution cycle, a fixed point fullword multiply requires two execution cycles, and a floating point long multiply requires four execution cycles with additional overhead if pre- or post-normalization is required.