Russell Jennings Lloyd

US Patent:

6643760, Nov 4, 2003

Filed:

Apr 30, 2001

Appl. No.:

09/845466

Inventors:

Bruce L. Troutman - Meridian ID
Russell B. Lloyd - Middleton ID
Randal Q. Thornley - Nampa ID

Assignee:

ZiLog, Inc. - San Jose CA

International Classification:

G06F 1200

US Classification:

711212, 711219, 36523003

Abstract:

The present invention provides a memory architecture allowing for instructions of variable length to be stored without wasted memory spaces. Instructions of one, two, and three bytes can all be retrieved in a single fetch. The exemplary embodiment divides the memory block into two Ã16 memories having some special addressing circuitry. This structure logically arranges the memory into a number of rows, each of four byte-wide columns. To the first of these Ã16 memories, the full address is provided. If the address is within the two columns of the second Ã16 memory, the full address is also provided to the second Ã16 memory. If the address is to the first of the Ã16 memories, the second Ã16 memory instead receives the portion of the address specifying the row with one added to it. This results in a dual row access with the last one or two bytes of 3-byte instruction being supplied by the row above the first byte. The net effect is that all the physical memory physical space is used for program code with none being wasted in the 24-bit access.

US Patent:

6970993, Nov 29, 2005

Filed:

Sep 8, 2003

Appl. No.:

10/658058

Inventors:

Bruce L. Troutman - Meridian ID, US
Russell B. Lloyd - Middleton ID, US
Randal Q. Thornley - Nampa ID, US

Assignee:

ZiLOG, Inc. - San Jose CA

International Classification:

G06F012/00

US Classification:

711212, 711219, 711102, 712205, 712210

Abstract:

The present invention provides a memory architecture allowing for instructions of variable length to be stored without wasted memory spaces. Instructions of one, two, and three bytes can all be retrieved in a single fetch. The exemplary embodiment divides the memory block into two ×16 memories having some special addressing circuitry. This structure logically arranges the memory into a number of rows, each of four byte-wide columns. To the first of these ×16 memories, the full address is provided. If the address is within the two columns of the second ×16 memory, the full address is also provided to the second ×16 memory. If the address is to the first of the ×16 memories, the second ×16 memory instead receives the portion of the address specifying the row with one added to it. This results in a dual row access with the last one or two bytes of 3-byte instruction being supplied by the row above the first byte. The net effect is that all the physical memory physical space is used for program code with none being wasted in the 24-bit access.

US Patent:

7570532, Aug 4, 2009

Filed:

Jul 26, 2007

Appl. No.:

11/881269

Inventors:

Russell Lloyd - Middleton ID, US

Assignee:

Zilog, Inc. - San Jose CA

International Classification:

G11C 7/02

US Classification:

36521014, 36518917, 365191, 365194, 36521012

Abstract:

A memory device includes memory cells that are overwritten in response to receipt of a clear request signal and an overwrite value. The clear request signal enables all word lines of the memory device to be overwritten. The clear request signal in combination with the overwrite value cause the overwrite value to be written to a first column of memory cells. At least two delay elements transfer the overwrite value to another column of memory cells after a delay. By use of at least two delay elements to delay and transfer the overwrite value to be written to another column of memory cells, a relatively low magnitude of current can be used to cause memory cells to be overwritten. In addition, the value and sequence of values that overwrite memory cells can be controlled.

US Patent:

7693418, Apr 6, 2010

Filed:

Aug 6, 2007

Appl. No.:

11/890457

Inventors:

Russell Brent Lloyd - Middleton ID, US

International Classification:

G03B 11/00

US Classification:

396544, 396422, 248690

Abstract:

This invention discloses a system to attach various photographic accessories to a camera by using an apparatus that attaches to the existing shoulder strap loop of a camera. The apparatus has a body, a strong hook to attach to the shoulder strap loop, and a thumbscrew that tightens the apparatus to the camera. The apparatus also incorporates an additional shoulder strap loop to replace the one covered when this system is used. Various mounting plates then attach to the body of the apparatus to which the various accessories are mounted.

US Patent:

20230072539, Mar 9, 2023

Filed:

Jul 29, 2022

Appl. No.:

17/877724

Inventors:

- Boise ID, US
David Roberts - Meridian ID, US
Russell B. Lloyd - Boise ID, US
William Tiffany - Eagle ID, US
Jeffery Tanner - Meridian ID, US
Terrence Leslie - Reva VA, US
Daniel Skinner - Meridian ID, US
Indranil Roy - Boise ID, US

International Classification:

G06N 3/063
G06K 9/62
G06F 9/38

Abstract:

Introduced here is an artificial intelligence system designed for machine learning. The system may be based on a neuromorphic computational model that learns spatial patterns in inputs using data structures called Sparse Distributed Representations (SDRs) to represent the inputs. Moreover, the system can generate signatures for these SDRs, and these signatures may be used to create definitions of classes or subclasses for classification purposes.