Ruth J Poole

US Patent:

7953957, May 31, 2011

Filed:

Feb 11, 2008

Appl. No.:

12/029045

Inventors:

Thomas M. Gooding - Rochester MN, US
Brant L. Knudson - Rochester MN, US
Cory Lappi - Rochester MN, US
Ruth J. Poole - Rochester MN, US
Andrew T. Tauferner - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/50
G06F 1/00

US Classification:

712 28, 712220, 713300, 718102

Abstract:

Methods, apparatus, and products for distributing parallel algorithms of a parallel application among compute nodes of an operational group in a parallel computer are disclosed that include establishing a hardware profile, the hardware profile describing thermal characteristics of each compute node in the operational group; establishing a hardware independent application profile, the application profile describing thermal characteristics of each parallel algorithm of the parallel application; and mapping, in dependence upon the hardware profile and application profile, each parallel algorithm of the parallel application to a compute node in the operational group.

US Patent:

8250383, Aug 21, 2012

Filed:

Apr 25, 2008

Appl. No.:

12/109579

Inventors:

Thomas M. Gooding - Rochester MN, US
Brant L. Knudson - Rochester MN, US
Cory Lappi - Rochester MN, US
Ruth J. Poole - Rochester MN, US
Andrew T. Tauferner - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/26
G06F 11/00

US Classification:

713300, 718104, 709226

Abstract:

A method of managing a process relocation operation in a computing system is provided and includes determining respective operating temperatures of first, second and additional nodes of the system, where the first node has an elevated operating temperature and the second node has a normal operating temperature, notifying first and second kernels respectively associated with the first and second nodes, of a swapping condition, initially managing the first and second kernels to swap an application between the first and the second nodes while the swapping condition is in effect, and secondarily managing the first and second kernels to perform a barrier operation to end the swapping condition.

US Patent:

8261249, Sep 4, 2012

Filed:

Jan 8, 2008

Appl. No.:

11/971006

Inventors:

Charles Jens Archer - Rochester MN, US
Thomas Michael Gooding - Rochester MN, US
Ruth Janine Poole - Rochester MN, US
Albert Sidelnik - Urbana IL, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/45
G06F 9/46
G06F 15/16
G06F 15/173

US Classification:

717149, 718102, 718104, 717150, 717159, 717160, 717161, 709201, 709226

Abstract:

Embodiments of the invention provide a method for deploying and running an application on a massively parallel computer system, while minimizing the costs associated with latency, bandwidth, and limited memory resources. The executable code of a program may be divided into multiple code fragments and distributed to different compute nodes of a parallel computing system. During program execution, one compute node may fetch code fragments from other compute nodes as necessary.

US Patent:

20110219208, Sep 8, 2011

Filed:

Jan 10, 2011

Appl. No.:

13/004007

Inventors:

Sameh Asaad - Yorktown Heights NY, US
Ralph E. Bellofatto - Yorktown Heights NY, US
Michael A. Blocksome - Rochester MN, US
Matthias A. Blumrich - Yorktown Heights NY, US
Peter Boyle - Yorktown Heights NY, US
Jose R. Brunheroto - Yorktown Heights NY, US
Dong Chen - Yorktown Heights NY, US
George L. Chiu - Yorktown Heights NY, US
Norman Christ - Yorktown Heights NY, US
Paul W. Coteus - Yorktown Heights NY, US
Kristan D. Davis - Rochester MN, US
Gabor J. Dozsa - Yorktown Heights NY, US
Alexandre E. Eichenberger - Yorktown Heights NY, US
Noel A. Eisley - Yorktown Heights NY, US
Matthew R. Ellavsky - Rochester MN, US
Kahn C. Evans - Rochester MN, US
Bruce M. Fleischer - Yorktown Heights NY, US
Thomas W. Fox - Yorktown Heights NY, US
Alan Gara - Yorktown Heights NY, US
Mark E. Giampapa - Yorktown Heights NY, US
Thomas M. Gooding - Rochester MN, US
Michael K. Gschwind - Yorktown Heights NY, US
John A. Gunnels - Yorktown Heights NY, US
Shawn A. Hall - Yorktown Heights NY, US
Rudolf A. Haring - Yorktown Heights NY, US
Philip Heidelberger - Yorktown Heights NY, US
Todd A. Inglett - Rochester MN, US
Brant L. Knudson - Rochester MN, US
Gerard V. Kopcsay - Yorktown Heights NY, US
Sameer Kumar - Yorktown Heights NY, US
Amith R. Mamidala - Yorktown Heights NY, US
James A. Marcella - Rochester MN, US
Mark G. Megerian - Rochester MN, US
Douglas R. Miller - Rochester MN, US
Samuel J. Miller - Rochester MN, US
Adam J. Muff - Rochester MN, US
Michael B. Mundy - Rochester MN, US
John K. O'Brien - Yorktown Heights NY, US
Kathryn M. O'Brien - Yorktown Heights NY, US
Martin Ohmacht - Yorktown Heights NY, US
Jeffrey J. Parker - Rochester MN, US
Ruth J. Poole - Rochester MN, US
Joseph D. Ratterman - Rochester MN, US
Valentina Salapura - Yorktown Heights NY, US
David L. Satterfield - Tewksbury MA, US
Robert M. Senger - Yorktown Heights NY, US
Brian Smith - Rochester MN, US
Burkhard Steinmacher-Burow - Boeblingen, DE
William M. Stockdell - Rochester MN, US
Craig B. Stunkel - Yorktown Heights NY, US
Krishnan Sugavanam - Yorktown Heights NY, US
Yutaka Sugawara - Yorktown Heights NY, US
Todd E. Takken - Yorktown Heights NY, US
Barry M. Trager - Yorktown Heights NY, US
James L. Van Oosten - Rochester MN, US
Charles D. Wait - Rochester MN, US
Robert E. Walkup - Yorktown Heights NY, US
Alfred T. Watson - Rochester MN, US
Robert W. Wisniewski - Yorktown Heights NY, US
Peng Wu - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/76
G06F 9/06

US Classification:

712 12, 712 29, 712 11, 712E09003

Abstract:

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.

US Patent:

20130159575, Jun 20, 2013

Filed:

Dec 15, 2011

Appl. No.:

13/327100

Inventors:

Thomas M. Gooding - Rochester MN, US
Brant L. Knudson - Rochester MN, US
Cory Lappi - Rochester MN, US
Ruth J. Poole - Rochester MN, US
Andrew T. Tauferner - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/24

US Classification:

710262

Abstract:

Power throttling may be used to conserve power and reduce heat in a parallel computing environment. Compute nodes in the parallel computing environment may be organized into groups based on, for example, whether they execute tasks of the same job or receive power from the same converter. Once one of compute nodes in the group detects that a parameter (i.e., temperature, current, power consumption, etc.) has exceeded a first threshold, power throttling on all the nodes in the group may be activated. However, before deactivating power throttling, a plurality of parameters associated with the group of compute nodes may be monitored to ensure they are all below a second threshold. If so, the power throttling for all of the compute nodes is deactivated.

US Patent:

20130159744, Jun 20, 2013

Filed:

Dec 6, 2012

Appl. No.:

13/706882

Inventors:

International Business Machines Corporation - Armonk NY, US
Brant L. KNUDSON - Rochester MN, US
Cory LAPPI - Rochester MN, US
Ruth J. POOLE - Rochester MN, US
Andrew T. TAUFERNER - Rochester MN, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 1/32

US Classification:

713320

Abstract:

Power throttling may be used to conserve power and reduce heat in a parallel computing environment. Compute nodes in the parallel computing environment may be organized into groups based on, for example, whether they execute tasks of the same job or receive power from the same converter. Once one of compute nodes in the group detects that a parameter (i.e., temperature, current, power consumption, etc.) has exceeded a first threshold, power throttling on all the nodes in the group may be activated. However, before deactivating power throttling, a plurality of parameters associated with the group of compute nodes may be monitored to ensure they are all below a second threshold. If so, the power throttling for all of the compute nodes is deactivated.

US Patent:

6658596, Dec 2, 2003

Filed:

Mar 13, 2000

Appl. No.:

09/523750

Inventors:

David Finian Owen - Rochester MN
Ruth Janine Poole - Rochester MN
Larry William Youngren - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1114

US Classification:

714 16

Abstract:

An apparatus, program product and method manage a queue through the use of element-based journaling to record changes made to logical elements in a queue. In contrast to convention memory-based journaling, where any changes to the memory representing an element in a queue are journaled, only those operations that affect the logical ordering and/or placement of an element on a queue, or the logical contents of such an element, are journaled. Memory management operations such as pointer manipulation operations that modify pointers or other memory management data, but do not otherwise modify the actual elements in a queue or their relative ordering, need not be journaled. As a consequence, the storage and processing overhead associated with journaling may be substantially reduced, thereby substantially reducing the overhead associated with maintenance and recovery of a queue.

US Patent:

20160011996, Jan 14, 2016

Filed:

Apr 30, 2015

Appl. No.:

14/701371

Inventors:

- Armonk NY, US
Ralph E. Bellofatto - Yorktown Heights NY, US
Michael A. Blocksome - Rochester MN, US
Matthias A. Blumrich - Yorktown Heights NY, US
Peter Boyle - Yorktown Heights NY, US
Jose R. Brunheroto - Yorktown Heights NY, US
Dong Chen - Yorktown Heights NY, US
Chen-Yong Cher - Yorktown Heights NY, US
George L. Chiu - Yorktown Heights NY, US
Norman Christ - Yorktown Heights NY, US
Paul W. Coteus - Yorktown Heights NY, US
Kristan D. Davis - Rochester MN, US
Gabor J. Dozsa - Yorktown Heights NY, US
Alexandre E. Eichenberger - Yorktown Heights NY, US
Noel A. Eisley - Yorktown Heights NY, US
Matthew R. Ellavsky - Rochester MN, US
Kahn C. Evans - Rochester MN, US
Bruce M. Fleischer - Yorktown Heights NY, US
Thomas W. Fox - Yorktown Heights NY, US
Alan Gara - Yorktown Heights NY, US
Mark E. Giampapa - Yorktown Heights NY, US
Thomas M. Gooding - Rochester MN, US
Michael K. Gschwind - Yorktown Heights NY, US
John A. Gunnels - Yorktown Heights NY, US
Shawn A. Hall - Yorktown Heights NY, US
Rudolf A. Haring - Yorktown Heights NY, US
Philip Heidelberger - Yorktown Heights NY, US
Todd A. Inglett - Rochester MN, US
Brant L. Knudson - Rochester MN, US
Gerard V. Kopcsay - Yorktown Heights NY, US
Sameer Kumar - Yorktown Heights NY, US
Amith R. Mamidala - Yorktown Heights NY, US
James A. Marcella - Rochester MN, US
Mark G. Megerian - Rochester MN, US
Douglas R. Miller - Rochester MN, US
Samuel J. Miller - Rochester MN, US
Adam J. Muff - Rochester MN, US
Michael B. Mundy - Rochester MN, US
John K. O'Brien - Yorktown Heighs NY, US
Kathryn M. O'Brien - Yorktown Heights NY, US
Martin Ohmacht - Yorktown Heights NY, US
Jeffrey J. Parker - Rochester MN, US
Ruth J. Poole - Rochester MN, US
Joseph D. Ratterman - Rochester MN, US
Valentina Salapura - Yorktown Heights NY, US
David L. Satterfield - Tewksbury MA, US
Robert M. Senger - Yorktown Heights NY, US
Burkhard Steinmacher-Burow - Beoblingen, DE
William M. Stockdell - Rochester MN, US
Craig B. Stunkel - Yorktown Heights NY, US
Krishnan Sugavanam - Yorktown Heights NY, US
Yutaka Sugawara - Yorktown Heights NY, US
Todd E. Takken - Yorktown Heights NY, US
Barry M. Trager - Yorktown Heights NY, US
James L. Van Oosten - Rochester MN, US
Charles D. Wait - Rochester MN, US
Robert E. Walkup - Yorktown Heights NY, US
Alfred T. Watson - Rochester MN, US
Robert W. Wisniewski - Yorktown Heights NY, US
Peng Wu - Yorktown Heights NY, US

International Classification:

G06F 13/28
G06F 9/38
G06F 9/30
G06F 15/80
G06F 12/08

Abstract:

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.