Ryan T Freese

US Patent:

7170774, Jan 30, 2007

Filed:

Feb 9, 2005

Appl. No.:

11/054479

Inventors:

Yuen H. Chan - Poughkeepsie NY, US
Ryan T. Freese - Poughkeepsie NY, US
Antonio R. Pelella - Highland Falls NY, US
Uma Srinivasan - Poughkeepsie NY, US
Arthur D. Tuminaro - LaGrangeville NY, US
Jatinder K. Wadhwa - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 11/00

US Classification:

365154, 365203

Abstract:

A domino SRAM array restore pulse generation system launches the word decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activation by releasing the reset signal (with the earliest arriving array clock, ckl), while guaranteeing almost perfect tracking with the bit decode system. This allows for the widest possible write window; earliest release of the pre-charge in the global column select, and resetting only after the bit decode system is deactivated.

US Patent:

7272030, Sep 18, 2007

Filed:

Oct 30, 2006

Appl. No.:

11/554072

Inventors:

Yuen H. Chan - Poughkeepsie NY, US
Ryan T. Freese - Poughkeepsie NY, US
Antonio R. Pelella - Highland Falls NY, US
Uma Srinivasan - Poughkeepsie NY, US
Arthur D. Tuminaro - LaGrangeville NY, US
Jatinder K. Wadhwa - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 11/00

US Classification:

365154, 365203

Abstract:

A domino SRAM array restore pulse generation system launches the work decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activation by releasing the reset signal (with the earliest arriving array clock, ck), while guaranteeing almost perfect tracking with the bit decode system. This allows for the widest possible write window; earliest release of the pre-charge in the global column select, and resetting only after the bit decode system is deactivated.

US Patent:

7293209, Nov 6, 2007

Filed:

Feb 9, 2005

Appl. No.:

11/054311

Inventors:

Yuen H. Chan - Poughkeepsie NY, US
Ryan T. Freese - Poughkeepsie NY, US
Antonio R. Pelella - Highland Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28

US Classification:

714724

Abstract:

A programmable delay circuit that delays the C clock signal by a variable amount that allows the output from the L latch to be captured even when there is a large delta between the L latch and its L latch. This allows the C signal to be adjusted within the system dependent upon the amount of cycle steal is needed. The C clock delay is inhibited during scan operation to prevent glitches and the trailing edge of the delayed C is controlled to maintain a constant C duty cycle.

US Patent:

7336546, Feb 26, 2008

Filed:

Feb 9, 2005

Appl. No.:

11/054309

Inventors:

Yuen H. Chan - Poughkeepsie NY, US
Ryan T. Freese - Poughkeepsie NY, US
Antonio R. Pelella - Highland Falls NY, US
Arthur D. Tuminaro - LaGrangeville NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 7/00

US Classification:

365190, 365154

Abstract:

A domino SRAM global bit select circuit provides an interface between dual global read and write bit line pairs to a “local bit select” circuit.

US Patent:

7463537, Dec 9, 2008

Filed:

Nov 1, 2007

Appl. No.:

11/933625

Inventors:

Yuen H. Chan - Poughkeepsie NY, US
Ryan T. Freese - Poughkeepsie NY, US
Antonio R. Pelella - Highland Falls NY, US
Arthur D. Tuminaro - LaGrangeville NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 7/00

US Classification:

365190, 365154, 365205

Abstract:

A domino SRAM global bit select circuit provides an interface between dual global read and write bit line pairs to a “local bit select” circuit.

US Patent:

20060176729, Aug 10, 2006

Filed:

Feb 9, 2005

Appl. No.:

11/054402

Inventors:

Yuen Chan - Poughkeepsie NY, US
Ryan Freese - Poughkeepsie NY, US
Antonio Pelella - Highland Falls NY, US
Arthur Tuminaro - LaGrangeville NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 11/00

US Classification:

365154000

Abstract:

A domino SRAM is provided with active pull-up PFET devices that overwhelm “slow to write but very fast to read” cells and allow the cells to recover from timing mismatch situations. This approach allows the traditional “bit select” clamp to actively control the “local select” through “wired-or” PFET pull-up transistors. Separate read and write global “bit line” pairs allow the read and write performance to be optimized independently

US Patent:

20220208234, Jun 30, 2022

Filed:

Dec 24, 2020

Appl. No.:

17/133956

Inventors:

- Santa Clara CA, US
Ryan T. Freese - Ft. Collins CO, US
Eric W. Busta - Ft. Collins CO, US

International Classification:

G11C 7/06

Abstract:

A sense amplifier is biased to reduce leakage current equalize matched transistor bias during an idle state. A first read select transistor couples a true bit line and a sense amplifier true (SAT) signal line and a second read select transistor couples a complement bit line and a sense amplifier complement (SAC) signal line. The SAT and SAC signal lines are precharged during a precharge state. An equalization circuit shorts the SAT and SAC signal lines during the precharge state. A differential sense amplifier circuit for latching the memory cell value is coupled to the SAT signal line and the SAC signal line. The precharge circuit and the differential sense amplifier circuit are turned off during a sleep state to cause the SAT and SAC signal lines to float. A sleep circuit shorts the SAT and SAC signal lines during the sleep state.

US Patent:

20230071807, Mar 9, 2023

Filed:

Nov 10, 2022

Appl. No.:

17/984796

Inventors:

- Santa Clara CA, US
Ryan T. Freese - Ft. Collins CO, US
Eric W. Busta - Ft. Collins CO, US

International Classification:

G11C 7/06

Abstract:

A sense amplifier is biased to reduce leakage current equalize matched transistor bias during an idle state. A first read select transistor couples a true bit line and a sense amplifier true (SAT) signal line and a second read select transistor couples a complement bit line and a sense amplifier complement (SAC) signal line. The SAT and SAC signal lines are precharged during a precharge state. An equalization circuit shorts the SAT and SAC signal lines during the precharge state. A differential sense amplifier circuit for latching the memory cell value is coupled to the SAT signal line and the SAC signal line. The precharge circuit and the differential sense amplifier circuit are turned off during a sleep state to cause the SAT and SAC signal lines to float. A sleep circuit shorts the SAT and SAC signal lines during the sleep state.